Sensor Interface Circuit And Power Management Circuit For Wireless Sensor Node Based On UHF RFID

With the development of sensor technology,the types of sensor is growing rapidly in recent years.Many challenges came up when they are used in wireless sensor nodes:more richer interface,lower power consumption and longer service life.When the wireless sensor nodes are applied to near or medium distance,the traditional solution(such as Zigbee or WIFI)will make the system more complex and more expensive.There are many advantages when UHF RFID is used as wireless sensor node,such as small volume,low power consumption,easy integration.And the communication distance(active mode 30m)is enough for most of the near or medium field data transmission needs.What's more,the cost of the semi active RFID is obviously less than other solutions.The wireless sensor node proposed by this thesis mainly composed of two parts:UHF RFID and high resolution SAR ADC.In order to quantify the sensing data,this paper introduces the design theory of a 10 bit100kS/s SAR ADC.To avoid the array area of SAR ADC capacitor being too large,the segmented capacitor structure are used.Then the influence of capacitor mismatch and parasitic capacitor are analyzed.Compromised between area and the accuracy,the bits ratio of MSB array and LSB array is set to 6:4.A new energy saving successive approximation algorithm is used reducing the power consumption of SAR logic.The function and effect are verified by Matlab model.To avoid the nonlinear distortion of the sampling switch,a bootstrap switch is used.Based on the sampling theory and operation method of bootstrap switch,the optimization method between switch size and performance are introduced.To avoid the effect of offset voltage,offset cancellation technique(OOS)is used which can effectively improve the resolution of the comparator.SAR control logic is realized by the state machine,and CMOS circuit are generated by using digital tools.Through the usage of Matlab model and simulation,the circuit performance are verified and met for the specifications.In order to achieve wireless wake-up function,this paper presents a wake-up circuit structure.By comparing the output voltage of rectifier with the reference voltage,a precision wake-up signal will be generate by the circuit.In order to meet the high sensitivity needs,a five stage Dickson charge pump are designed using Native MOS.In order to reduce the static power consumption of reference circuit,a ultra-low power reference named 4-V_T reference are used.It is composed of only 4 MOS transistors operating at subthreshold region cost only Pico watts.To avoid the static power consumption of continuous comparator,the periodic regenerated comparator(Latch)is used.In order to provide control signal for Latch,a low power ring oscillator based on the principle of subthreshold leakage current is used.In order to improve the communication distance,an active demodulation circuit is used which can operate at-25dBm RF input power.The decode circuit mainly composed of compensated MOS,peak-detect circuit and hysteresis comparator.All the circuits mentioned above are designed using SMIC 0.18?m process and simulated by Cadence.The simulation results prove the design meet the demand of wireless sensor node.