Design And Implementation Of An Improved Non-homogeneons Bandwidth Digital Channelizer

As the key technology of future satellite communication systems,the digital channelizing can divide the satellite link into multiple sub-channels and implement the precise extraction,exchange,and reconstruction of user signals according to the channel division,as well as the flexible exchange of both uniform and non-uniform bandwidth signals.This thesis focuses on studying the implementation of a non-uniform bandwidth digital channelizer,and completes the design of the system on the FPGA while ensuring that its functionality and bit error performance is good.The main work of this thesis is summarized as follows: 1.Based on the complex exponential modulation filter bank technique and the frequency domain filter,an improved implementation structure of the non-uniform bandwidth digital channelizer is presented.The data processing structure of the M sub-channels is simplified to the structure of two compound channels,and the complexity of the implementation is reduced while it can still implement extraction,reconstruction and other functions of signals.2.The performance of the prototype filter determines whether the digital channelizer can achieve the reconstruction requirements of user signals.Considering the need to reduce the hardware resource consumption,this thesis selects the suitable order of the filter through the parameters set by the system.Combining the frequency sampling method and Kaiser window function method,a prototype filter with large stop-band attenuation and good pass-band stitching performance is designed and verified by its performance simulation.3.A simulated model of the improved digital channelizer is set up to simulate the terms of the power leakage between the adjacent sub-channels and the bit error performance of the different modulations(BPSK,QPSK and 8PSK)and FFT operation points.Because of the need to implement the system on the hardware,whether the quantification of signals and filter coefficients can affect the performance of the system is also simulated.Simulation results show that the leakage power between the adjacent sub-channels is less than-75 dB,which basically doesn't affect the reconstruction of user signals.Compared with the ideal case,the bit error performance of the system is minimally degraded,even the performance degradation of the digital channelizer after quantification is still less than 0.3dB to meet requirements of the system.4.According to the different functions,the improved digital channelizer system is divided into several modules.Then the FPGA design of each submodule is completed and their functions are simulated.Finally,the function of the whole digital channelizer system is simulated and compared with the simulated model of MATLAB to verify its performance.