Research On The Timing And Positioning Method Of Beidou Receiver

With the rapid development of satellite navigation technology,It has been widely used in military's and livehood's many fields.Which makes great significance for both of People's life and national defense.Our country began to energetically develop our own navigation technology since the last century,the Beidou system has go through the development of generation I and II,By the end of 2012,it has been able to provide services to the AsiaPacific Region.At present the construction of the three generation is in full swing,the development and improvement of Beidou system has become a hot point as well.The Beidou system includes Space satellites,Ground control platform and User receiver,Among them,Research on the Beidou receiver is the most widely.The improvement of Beidou receiver's timing and positioning method is varied.Compared to the mesure such as the ameliorate satellite selection algorithm and the antenna optimization,the process of Beidou receiver's baseband signal is the key to decide the performance of the receiver system.This paper builds up a portable Beidou receiver system,it put the Farrow structure which is based on Lagrange interpolation algorithm and can be implemented in hardware in the Code tracking module,and then make the structure simplified.At last,download it to the FPGA.In order to adapt to the complex environment,improve the utilization rate of bandwidth,the Beidou satellite navigation system adopts CDMA spread spectrum communication technology,which has strong anti-interference ability.In this technology,We modulate navigation message with Range C code.In order to despread the signal,The local range C code produced by the Beidou receiver need to tracking the signal accurately and quickly.By this way,the speed and accuracy of positioning can be improved.In this paper,we focuse on the problems of traditional phase-locked loop(PLL)design,the All-digital demodulation technology based on the Interpolation filtering algorithm is applied to the symbol tracking module of Beidou signal.The technology adopts a digital open-loop structure with no phaselocked loop and no feedback loop.The local reference carrier and sampling clock used for demodulation oscillate at a fixed frequency,further improving the timing and positioning rate of the Bei Dou receiver.Then based of it,we initially build the software and hardware systems of the Beidou receiver.In this system,In the two-dimensional plane positioning we use Beidou/GPS navigation/timing service dual system,The height orientation is based on the rule that the atmospheric pressure decreases as the altitude increases,and it is converted it into physical height by a mathematical fitting method.Two-dimensional plane positioning plus height parameters makes three-dimensional positioning achieved.By analyzing the data obtained from the satellites,then,accurate time and date can be obtained after the conversion.At last,the timing function can be achieved.In the code tracking loop,the sampling frequency and the code rate of the signal are independent to each other,The system uses the timing error estimation value to control the interpolation filter to perform interpolation operation on the sampled signal to achieve synchronized tracking of the pseudo code.By this way,we can recover the data codes more quickly and efficiently for parsing location and time information.In order to achieve the goal of quick positioning and timing.In this system,we selected STEVAL-MKI062V2 based on MEMS devices and controlled by STM32F103 RET which was produced by STMicroelectronics as the MCU,to centralize manage and coordinate the work of each module and analyze signal.The air pressure value is converted to altitude data via the LMS pressure sensor LPS001 DLA,which is provided on the MCU,for elevation positioning.LPH7366 LCD screen was used as a display module.Among them,the baseband signal processing module adopts the Farrow structure which was based on Lagrange polynomial interpolation filter.Verilog HDL programming is performed on the Farrow structure.and its signal processing abstraction algorithm is established in the context of MATLAB/Simulink,then the XILINX System Generator for DSP is linked to generate a parameterized module for FPGA hardware implementation.Finally,the entire algorithm was downloaded to the hardware Cyclone III EP3C16F484C6.