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Research Of FPGA Implementation Of QPSK Neural Network Demodulation Algorithm

Posted on:2019-05-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y ShenFull Text:PDF
GTID:2428330572950306Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
In recent years,communication technology has made rapid progress.As an important part of communication system demodulation has been widely applied.Many non-ideal factors,such as frequency offset,time offset and multipath effect,are introduced in the process of transmission and reception.These factors have higher requirements for the performance of demodulation.In the traditional demodulation system,the logic is more complex,there are a large number of configurable parameters,resulting in the poor robustness of the demodulation system,and the traditional demodulation methods are mostly general type,and are less adaptable to the special conditions such as frequency offset and time offset.Convolution neural network is a kind of artificial neural network.It has low requirement for input information pretreatment,high accuracy of feature extraction and autonomous learning ability.One dimensional convolutional neural network is especially suitable for discrete time series processing because of its unique one-dimensional structure characteristics.Therefore,this paper proposes the use of one dimensional convolutional neural network to realize the demodulation of QPSK(Quadrature Phase Shift Keying).By constructing a suitable network structure,the robustness of the demodulation system can be improved.Through proper training,the demodulator can improve the adaptability of the demodulator to the special conditions such as frequency offset and time offset.In this paper,the characteristics of the QPSK modulation signal are analyzed.On the basis of the information contained in the QPSK modulation signal is included in the relative phase shift,the relative phase shift is regarded as a feature,and the one dimension convolution neural network is used to detect the feature,so the demodulation can be realized.On the basis of repeated experiments,the optimal network structure is given,and the training process of network is explained.Then,this paper proposes an FPGA(Field Programmable Gate Array)implementation scheme for QPSK demodulation algorithm based on one dimension convolution neural network.It mainly describes the whole architecture of FPGA implementation and the most important relative phase shift detection module.A time delay network is used in implementation of one dimension same convolution kernel.The realization method of sigmoid activation function based on piecewise fitting is introduced.The time sharing method of network,the selection of data precision and quantization method,the pipeline and parallel structure of the system are also introduced.Through the above methods and structures,the amount of computation in the FPGA implementation process is reduced,and the efficiency of hardware resources is improved.The results of FPGA implementation of the algorithm are tested in this paper.Firstly,the construction of the test platform is explained.Then the production process of the training data is introduced in detail,and then the implementation are tested,including three aspects:the influence test of the length of the input vector and the number of hidden layer neurons to the demodulation performance,the test of the sampling,and the BER(Bit Error Ratio)test under the condition of AWGN(Additive White Gaussian Noise).Finally,in the same hardware platform,this paper compares the demodulation algorithm with a common coherent demodulation algorithm in four aspects: resource occupancy,power consumption,delay and frequency offset.The results show that under the condition of AWGN channel,the loss of neural network demodulation can almost remain within 2d B.Compared with coherent demodulation algorithm,neural network demodulation algorithm has shorter delay and better adaptability to frequency offset.
Keywords/Search Tags:convolution neural network, demodulation, FPGA, QPSK
PDF Full Text Request
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