The Design And Research Of Variable-k Dielectric Trench LDMOS Structure

In integrated circuits,lateral power semiconductor device LDMOS is considered as a core device.There is the biggest limitation,which is the larger cell area and the "silicon limit"of the material itself.Compared to vertical devices,the increased drift region length when the LDMOS increases the withstand voltage will be directly reflected in the device drift.The most effective and most commonly used technique for shortening the lateral device size is the trench technology,but the device with the trench is often limited by the characteristics of the trench dielectric itself and cannot perform the perfect device performance.Combining variable-k with trench technology can highlight the advantages of variable-k dielectrics when reducing device drift,and improve itsperformance.The paper theoretically analyzes variable-k technology.The advantages of combining trench technology,the following two structures are proposed:? VK DT-P LDMOS with dual variable-k trenches and dual RESURF vertical P-columns.? VFP HK LDMOS with high K dielectric trenches,vertical gate field plate(VFP),and high concentration N+,which can increase the device breakdown voltage while reducing its specific on-resistance to break the "silicon limit".1.The VK DT-P LDMOS with dual conductive channels is proposed,which is based on the enhancement of the electric field by a low dielectric constant.The low K dielectric material in the upper half of the variable-k double trenches can greatly increase the surface electric field of the trench and improve the withstand voltage of the device.At the same time,the silicon dioxide filled in the lower half of the trench can reduce specific on-resistance.The vertical P pillars are introduced between the dual trenches utilizing dual RESURF technology,which can extend the equipotential lines to the bottom of the drift region,to fully utilize the device drift region,while modulating the device body electric field to further increase the device breakdown voltage.Significantly increase the specific resistance in the drift region.The dual conductive channel provides two current paths that significantly reduce the specific on-resistance.Simulation data analysis shows that devices with a length of only 17?m can achieve breakdown voltages up to 555V and low specific on-resistance of 13 m?·cm2.The breakdown voltage of VK DT-P LDMOS is 104%higher than that of the conventional structure,and the specific on-resistance is 87.9%lower than that of the conventional structure.At the same time,the VK DT-P LDMOS will be discussed and the layout design will be made in this paper.2.Based on the concept of high-dielectric-dielectric polarization charge self-equilibrium,a VFP HK LDMOS with a high-K dielectric trench,a VFP,and a high-concentration N+low-resistance channel is proposed.The structure introduces a high dielectric(K)trench in the drift region and introduces a high-concentration N-type doped low-resistance channel at the interface under the high-k trench,while introducing a VFP in the high-k trench.In the on state,A strong electron accumulation layer is formed on the upper and lower sides of VFP,which reduces the specific on-resistance of the device.The introduction of the parallel gate provides another current path to lower the specific on-resistance again,and,the existence of the N+low-resistance channel allows specific on-resistance to be further reduced.In the off state,the high-k trench and VFP simultaneously make the horizontal transition of the power line,and then ultimately point to VFP and part of the parallel gate,which greatly increases the breakdown voltage.The simulation results show that the VFP HK LDMOS has a withstand voltage of up to 629.1V,a specific on-resistance of 38.4m?·cm2,and a power value(FOM)of 10.31MW·cm-2.Compared with the Con.LDMOS,the withstand voltage and the FOM increases by 61.8%and 910%,respectively.Compared with the HK LR LDMOS,the on-resistance decreased by 53.6%,and the FOM increased by 102.6%.And this paper explores the design of the process and layout of the VFP HK LDMOS.