Design And Implementation Of Architecture For Real-time 3D-filtering Of High Definition Video

Along with the technical unceasing progress,the demand for the quality of the images obtained is constantly improving.However,in the process of actual acquisition and transmission,noise is inevitably introduced into video and image and it affects the visual experience of the audience,so the denoising becomes an indispensable part of image processing system.On the other hand,as it is an essential step in image visual preprocessing,image denoising determines the accuracy of application of many post-processing algorithms such as visual enhancement,feature extraction,target recognition and target segmentation.In view of the increasingly demand for high definition video and image denoising,this paper studies and analyzes the existing classical image denoising algorithm and related hardware acceleration design both at home and abroad.BM3 D algorithm with the state of the art denoising performance in the actual scenario is studied in detail.The main work of this thesis include:(1)The principle of BM3 D algorithm is analyzed and the experimental analysis and comparison of adjustable parts,including various parameters,transformation types and aggregation methods,are presented.(2)According to the requirement of low noise variance and real-time processing in the actual video acquisition system,this paper improves each step of the BM3 D algorithm for hardware-oriented design and proposes a fast 3D-filtering denoising algorithm.And,we analyze the advantages and disadvantages of the proposed algorithm based on the experimental results.Due to the inadequacy of filtering in the homogeneous region,the algorithm is further improved by introducing the block mean filtering and a fast 3D mean filtering denoising algorithm is proposed.In order to evaluate the performance of the final improved algorithm,we select objective PSNR and SSIM and subjective visual evaluation experiment.Experiment results show that our proposed algorithm is stronger than that of the classical NLM and K-SVD in the denoising performance and has lower complexity.(3)Based on the proposed denoising algorithm,we design a low cost efficient parallel fully pipeline hardware architecture.The architecture is divided into four stages: block extraction,block matching,3D mean filtering and aggregation.Seamless connection between all level of pipeline is realized in parallel operation,and data reuse is fully exploited which not only reduces the storage access bandwidth but also reduces the resource consumption.The architecture is implemented by Verilog hardware description language after module division from top to bottom and verified by simulation.The comparison between hardware simulation results and software results shows that the hardware architecture proposed in this paper has the same denoising accuracy as the software processing result.The architecture has a maximum working frequency of 279 MHz on Xilinx Zynq-7000 FPGA and its maximum input resolution is 4K(3840×2160),the throughput can reach up to 4K@33fps,the resource occupancy rate is only 16%,and any external memory for intermediate data cache is not required.To sum up,a fast 3D mean denoising algorithm is proposed based on BM3 D algorithm for hardware structure design,which has low computational complexity with excellent denoising performance.Based on the algorithm,an efficient parallel full-pipeline hardware architecture with high accuracy,high throughput,low cost and flexibility is proposed which can totally satisfy the requirement for high definition video with real-time and efficient denoising in the practical application.