Design Of High-definition Video Defogging System On FPGA

With the establishment and improvement of 5g infrastructure,the security and defense system,urban traffic system and some others will be upgraded futher,so it's high quality requirements for the video images.However,in haze weather,due to the scattering and absorption of light by suspended particles,the contrast and color saturation of the video collected by the equipment will decrease to some extent,which will affect the subsequent image processing tasks,bring difficulties to the practical application scenarios such as video monitoring,intelligent transportation,aerial photographing and automobile navigation.In addition,the current research on defogging is mainly in the aspect of single image defogging,most of which are implemented by software on PC platform,which is difficult to meet the requirements of high resolution and high real-time.Therefore,research on real-time defogging of high-definition video has high application value.This thesis takes the real-time defogging of high-definition video as the goal,and takes advantage of the parallel computing of FPGA hardware platform to design a set of highdefinition video defogging system with low cost,excellent defogging effect and processing speed to meet the resolution of 1920×1080p@60Hz.First of all,this thesis introduces in detail the current domestic and foreign research in the field of defogging and the significance of video defogging.Aiming at the characteristics of various processors,this thesis chooses FPGA hardware platform to implement video defogging,and analyzes the current FPGA-based video defogging Research progress.Secondly,this thesis derives the process of atmospheric scattering model establishment and conducts in-depth research on the single image defogging algorithm based on Dark Channel Priors,summarizes the implementation steps of the algorithm for the Guided Image Filter to refine the transmittance,and analyzes the effect of some parameter settings on the processing results during the implementation process and the causes of halo on the edge of dehazing and white area processing distortion.Then,this thesis improves the original algorithm based on FPGA characteristics and video defogging ideas,and designs a hardware defogging architecture.On the basis of summarizing the realization ideas of video defogging,detailed analysis of FPGA hardware characteristics and the limitations of accelerated defogging,this thesis combines FPGA computing characteristics and the correlation between video frames to improve some of the calculation methods in the defogging algorithm based on Dark Channel Prior.Including:using histogram statistics to calculate the threshold and linearly correct the atmospheric light value,propose a two-scale minimum difference filter to refine the dark channel map to reduce the halo effect,and design a hardware-side sky area detection and transmittance compensation Method,and then determine the overall architecture of the HD video defogging system in this thesis.Finally,this thesis designs the FPGA hardware platform of the defogging system based on hardware indicators,introduces the design of each hardware circuit and the board-level test method of this thesis in detail.The code of each sub module in the video defogging logic and the frame buffer output display logic is written and simulated.This thesis gives the logical structure and circuit design of the key modules in the structure,testes and analyses the system's effect and other functions on the FPGA platform with the real shot renderings to realize the high-difinition resolution of 1920×1080p@60Hz video defogging processing.