| Direct Memory Access(DMA)technology is a data transmission technology with high speed and high efficiency for data transmission between modules.When carrying out data transmission tasks of DMA type,designers need to design a DMA controller as the main controller of the control process in the transmission process.Before starting the data transfer task,CPU need configure the information of the DMA controller for task initialization,and then the DMA controller can read and write the data directly on the corresponding storage address according to the configured information,and no longer need CPU intervention.Therefore,this way of transmission greatly saves the resources of CPU,and greatly improves the efficiency of data transmission.With the faster running rate of CPU,more and more data transmission in the system,more and more complex,the research and design of DMA controller will be the most important thing to improve the performance of the system.The purpose of this paper is to design a DMA controller based on AHB(Advanced High-performance Bus)bus protocol.First of all,I learned the development trend of memory access technology at home and abroad by consulting the data.Through the in-depth study of the AHB bus protocol,the key technical indexes of the AHB bus protocol are summarized,and the basic principle of the DMA data transmission mode is deeply studied.In view of the actual requirements of the engineering design,the design scheme of a fully functional DMA controller is proposed,and the system function sub modules of the DMA controller module are further divided according to the design scheme,including the core logic,the state machine and the interface module,and the performance level description of DMA controller is detailed descriped in the Verilog HDL language.After the design is completed,the verification platform is built under the System on Chip(SOC),the design code is integrated into the verification environment.After the compilation of the electronic design automation(EDA)tool,the single function and time series verification of its sub modules is carried out,and carried out many debugging and modification.Then,the whole function and timing simulation is verified for the top level instantiation module.The verification results show that the data transmission is accurate,the signal transmission timing meets the design index,code coverage results are fully covered and the DMA data transmission task is successfully completed. |
