Design And Verification Of Host Controller For EMMC5.1 Protocol

The rapid integration of communication technology,network technology and big data technology puts forward higher and higher requirements for the capacity and stability of storage hardware system.due to its short life,high error rate,slow speed of read and write,poor stability faults,conventional NAND Flash chip can be erased already cannot satisfy the current demand for storage hardware,It is urgent to design memory chips with higher reliability and better performance to replace NAND Flash chips.Under this background,embedded multimedia card chip eMMC came into being.In recent years,eMMC has developed rapidly and its performance has been continuously improved.It has successfully occupied the high-end market such as smart phone and tablet computer.However,in China,the design of host controller conforming to standard protocol is still in a relatively backward stage.Based on this situation,a host controller is designed according to the eMMC5.1 protocol standard to meet the requirements of high speed and large capacity real-time data communication between SoC chips and eMMC devices.In this thesis,the protocol specification of eMMC5.1 is deeply studied,and a complete eMMC host controller design scheme is proposed,and the main sub-modules covered by the host controller are carefully designed and analyzed,and the overall hardware design is also simulated and verified.The main innovations of this study are as follows:(1)due to the large capacity of eMMC data transmission,two 512Bytes ping-pong RAM are integrated in the main control to reduce the delay of data transmission and improve the data transmission efficiency inside the main control.(2)The host controller is equipped with a clock management module,which provides flexible clock switching for the device in different working modes and outputs a stable transmission clock;(3)Due to the small disturbance caused by chip operating voltage or operating temperature and other factors,the clock frequency at that time is very high(HS200/HS400 speed mode).The data received by the master control is difficult to align with the sampling clock,that is to say,the timing relation of sampling cannot meet the requirements,which is easy to cause transmission errors.In order to ensure correctness of data transmission,The timing regulation module is introduced to adjust the host.In this thesis,a language is employed to design circuit in the style of RTL code,that is also called Verilog,and the simulation tool NC is used for strict function simulation verification to ensure the accuracy of the hardware circuit design.The simulation results show that the host controller achieves the expected function and timing,can give full play to the characteristics of eMMC5.1,and completes the logic synthesis of RTL code through TSMC 28 nm CMOS process library.The design area of the whole controller is about 369,619 μm2.The implementation of functional timing and logic is of practical significance to improve the performance of storage hardware.