Study On Sneak-path Issue And Line Resistance In Resistive Random Access Memory

With the increasing demand for higher capacity and higher speed in computer systems,traditional silicon-based memories will reach their miniaturization limitations in the near future.As a new type of non-volatile device,RRAM(resistance random access memory)is attracting considerable attention from researchers due to several advantages such as simple structure,high density,low power dissipation and high operation speed.RRAM integrated in crossbar array architecture will replace semiconductor devices and change the existing computer systems in industry revolution of information storage and high-speed computing.However,some problems such as sneak-path issue and line resistance have hindered the further development of RRAMs and their effects will be aggravated when size and density increase.Therefore,it is necessary to propose solutions to these problems to improve read or write performance.We focus on the study of these two problem and main contents of this dissertation are illustrated as follows:In chapter 2,studies on sneak-path issue and line resistance are reviewed,and the shortcomings of existing studies are summarized.In chapter 3,the crosstalk phenomenon is studied based on 1D1R crossbar array.Firstly,this paper introduces parameters of 1D1R cell in Section 3.1 and builds models of 1D1R cell and cross point RRAM array in Section 3.2.The classical 1/2-and 1/3-bias schemes in the 1D1R crossbar array are studied,and an u_D/2 bias scheme is proposed based on diode's asymmetric resistance characteristics in Section 3.3.In this scheme,the value of bias voltage source is determined by the forward voltage drop on the diode of 1D1R cell.Therefore,the voltage across the unselected cell is lower than the half of its forward voltage,significantly reducing the impact of sneak-path issue.In chapter 4,based on 1D1R,this paper investigates the line resistance in crossbar array and proposes a single-bit write operation method with voltage source coefficient adjustment algorithm in Section 4.3.In this method,the line resistance on conductive path is calculated for the certain location of the selected cell in array and the voltage factor of corresponding source is adjusted based on its voltage division ratio.So the actual voltage drop on the selected cell is as same as the expected write voltage,alleviating the impact of line resistance on the write operation effectively.For multi-bit parallel operation,a co-wordline multi-bit write method is proposed by means of adding serial compensatory resistors on bitlines and adjustment on voltage coefficient in Section 4.4,reducing the impact of line resistance on writing multi-bit data simultaneously.