Research On Technologies Of High Efficiency On-Chip Network For GPGPU

With the continuous development of semiconductor process technology,microprocessor design has been gradually from signle-core to multi-core and all-core processor development,integrated the resources of computing on th chip more and more.GPGPU as a simple typical multi-core stream processors,because of its excellent computing performance potential has been widely used in the life of sciences,graphics,vision and signal processing and other high-performance conputing and scientific conputing.GPGPU communication is different with the general CPU,which data transmission only exists between the computing node and control node,and the other nodes do not exist between the communication.With the increase of on-chip Cores,more and more conputing nodes need to realize the data interaction with the control nodes through the on-chip network,and the architecture of GPGPU design will alse face with many problems,such as over-network hardware overhead-Large,low utilization of network resources and data transmission reliability issues et.How to design a GPGPU-compliant network is crucial to the development of GPGPU,which will greatly restrict the performance of th systems.The main work and innovation of this paper are as follows:(1)A dynamic virtual channels partitioning mechanism(AD-VC)for GPGPU on-chip network was proposed.We analyzed the unbalanced distribution of GPGPU on-chip network resources,and a multi-virtuals dynamic partitioning mechanism for multi-ports router was designed.The state of initial and state of sampling and state of runing were included.The central decision module was designed by adding a small amount of hardware overhead.It was responsibled for the dynamic collection of the proportion of the on-chip network message types,according to the optimal system performance under different configurations in the sampling state,and then determined the virtual channels in the on-of the best configuration.By improving the utilization of network resources,GPGPU could get the more higher performance of system.(2)The GPGPU low overhead conflict-free reply network design scheme(MR_mesh)was propoed.We proposed a low-overhead on-chip network design for the characteristics of the communication network in GPGPU and the different characteristics of the storage nodes and the layout of the conpute nodes in this paper.The computing nodes and control nodes were divided into several groups to analyze the conflict between the nodes sending the reply packets to the different compute node groups.The authorization discrimination moduel was designed to authorize and control th issuing of eachnode.And the low-overhead microarchitecture of router was designed to realize the single-shot transmission delay between adjacent routers.The above design schemes were implemented on the GPGPU-Sim simulator,and the performance of system was tested and analyzed according to ISPASS [38] and Rodinia [42] test of set.The experimental results showed that the AD-VC could achieved higher performance of system;while the MR_mesh network could reduced the area and power consumption at the expense of a small amount of performance.