| With the development of microelectronics technology, more and more IP corescould be integrated on a single multiprocessor System-on-Chip (SoC). The traditionalSoC shared bus architecture does not meet the need of multi-IP system development. Tosolve this problem, a new on-chip interconnection architecture called Networks-on-Chip (NoC) is proposed by referencing the computer network technology. NoC realizesthe separation of communication module and computation module, has good parallelcommunication capability, and solves the shortages existed in SoC such as lowexpansibility, low communication efficiency, high power consumption due to globalsynchronization. NoC has become a design trend for on-chip interconnections.With the reduction of feature size and higher frequency, NoC becomes moresensitive and unreliable to the noises caused by crosstalk, electromagnetic interferenceand voltage disturbance, etc. At the same time, the possibility of faults which occurs inmanufacturing process or operational phase increase as transistor density on IC becomeshigher and higher. Therefore, the fault tolerant technique for NoC has become a researchfocus in the related field. With the fault tolerant routing as the research prototype, thisdissertation focuses on fault tolerant routing algorithm without virtual channels andsimulation platform design of NoC. Some novel and practical results are also gained inthis paper. The main contributions are summarized as follows:1. Single fault NoC tolerant algorithm without virtual channels has been studied.On basis of analyzing the structure of single fault NoC, a novel tolerant routingalgorithm is proposed to solve the deficiency of using existing algorithms in single faultNoC routing. By setting new auxiliary nodes and the optimized fault tolerant strategy,the network load can be balanced and the transmission delay is reduced. Moreover,deadlock free behavior of it is proved. Static and dynamic simulation results show thatproposed algorithm has the advantages of less power consumption and low delay.2. Multiple faults NoC tolerant algorithm without virtual channels has been studied.With consideration of the problems of the existing algorithms, a novel fault tolerantrouting algorithm without using virtual channels for2D Mesh NoC is proposed. Therouter design is presented, and then optimization methods and implementation steps ofproposed algorithm are discussed. On this basis, its deadlock freeness is proved usingChannel Dependency Graph (CDG) theory. Simulation results show that the proposedalgorithm can reduce communication latency and has better performance when the faultarea increases. 3. Links fault model based NoC tolerant algorithm without virtual channels hasbeen studied. According to the deficiency of both larger fault region and low utilizationratio of nodes that exists in the nodes fault model, a novel fault tolerant routingalgorithm without using virtual channels based on links fault model is proposed.Because of using the new model and the optimized fault tolerant strategy, detourdistance of faults can be reduced and utilization ratio of nodes can be increased.Simulation results show that the proposed algorithm can reduce transmission delay andincrease network throughput.4. Development and application of the NoC simulation tool. By carrying on themodeling of the network domain, the node domain and the process domain in OPNET, amodular software simulation tool—OBNSP (OPNET Based NoC Simulation Platform)is constructed. We can use the models base of the platform to make simulations of NoC.The platform also supports secondary development, and the new topology, the routerarchitecture and the routing algorithms can be added by modifying correspondingmodules.5. Design and Implementation of NOC hard ware emulation and evaluationplatform. Introduce the design methods and structure of the two hardware platforms.Simulations of the NoC topology, the router architecture and the routing algorithms canbe realized. |
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