Study On Thermal Analysis And Temperature Prediction Model Of 3D Stacked Chips

The packaging of 3D stacked chips has become the main trend of the development of the system in package(SiP)technology.However,compared with the conventional single chip packaging,the stacked packaging encapsulates more dies,where internal heat sources interact and the thermal coupling is stronger,which could make the internal stacked chip thermal field is more complex than the monolithic integrated circuit,and may cause more serious reliability problems.Accurate prediction of the temperature of stacked chip with the power of each die will have great significance for the design of the chip's thermal reliability and the evaluation of the thermal performance of the chip itself.Based on the JESD51-2 standard,this thesis uses a well-designed 6-layer die to perform thermal test experiments.The method of indirectly obtaining the temperature of the chips by measuring the resistance of the temperature-sensitive resistance line is used to study and analyze the heat flow path of the stacked chips.FloTHERM thermal simulation software is used to establish a thermal simulation model of the stacked chips,and analyzes the thermal field distribution of the stacked chip from the perspective of simulation.And the infrared thermal imaging experiment of stacked chips is carried out,and the infrared temperature measurement results and simulation results are compared,it is conformed that the simulation model established is reasonable.A thermal resistance matrix method for predicting stacked chips temperature based on the principle of thermal linear superposition is proposed.It is also proposed that the thermal resistance network model based on the internal stack structure of the chip.The experimental data analysis proves that these two methods can predict the temperature of the stacked chips correctly.The experimental data are analyzed to verify the correctness of the two methods to predict the temperature of the stacked chips.In this thesis,four factors and three levels of orthogonal experiments are used and the effects of the factors of the thickness of stacked die,die's thickness,die's area,die's layer number on the heat dissipation performance of the stacked chips are studied through simulation.It is found that the chip area is the most significant factor affecting the heat dissipation of the chip,and a good heat dissipation lamination structure is determined.The temperature of each layer of dies under the test conditions of high temperature(125?)and temperature cycling(-65?~150?)is measured.And the degradation rule of the heat dissipation performance of stacked chips under high temperature and temperature cycling test is studied.It is found that the heat dissipation performance of the chip is faster in the early tests than in the later period.The thermal performance of the top chip is more degraded than that of other layers.