FPGA-based Virtual Platform Hardware Simulation Acceleration Unit Design

With the continuous development of integrated circuit design technologies and manufacturing processes,the complexity and scale of on-chip systems are also increasing.Traditional serial development methods of hardware and software have been difficult to meet the time-to-market requirements.The virtual platform provides a feasible solution for the collaborative development of hardware and software.By using a high abstraction level language to model the hardware,not only can the system architecture be explored,and can use the model of the hardware to develop software.Parallel development of hardware and software design can be realized,and the time to market is shorten.The virtual platform focuses on the functional consistency and there is a certain gap with the real hardware in behavior and speed.FPGA has high efficiency and authenticity in hardware simulation.Therefore,the combination of virtual platform and FPGA unit can provide more abundant functions and has important research significance.In this paper,the QEMU and FPGA unit are combined to form a hybrid virtual platform,using Gigabit Ethernet to achieve communication between the two parts.The design of the platform is mainly divided into two parts: the QEMU,which is the main part of the virtual platform,can be used to model the CPU,bus,memory,and various peripherals.By adding an interface device to represent the FPGA unit,QEMU can use Raw Socket to transfer transaction with FPGA;The target IP core in FPGA can be controled and accessed by building SoPC.The hardware part includes control unit and user-defined logic unit.The software environment of control unit realizes transmission,analysis and processing of Ethernet frames.Finally,this paper designs a configuration mechanism for the virtual platform.By using the device tree to describe the hardware and using coroutine mechanisms to analyze it,and of each device of the virtual platform can complete the initialization and configuration process.Finally,basic functional verification and performance testing for the virtual platform is carried out.The device tree is used to describe a complete system and it can be started successfully.This QEMU is the main control part of the system,including the model of CPU,bus,memory,UART,interrupt controllers,and other devices.The user logic is added as target IP core in FPGA,such as image codecs module.The results show that the virtual system can run normally and realize the system-based simulation of the target IP core described by RTL.Compared with the software simulator,it shows obvious simulation acceleration effect for complex IP.