Research On The Key Technology Of PUF Circuit Design For Information Security Chip

As a trusted platform module(TPM),the security chip plays an very important role in feature data generation and storage,sensitive data encryption and decryption,and security authentication.However,with the continuous development of chip attack technology,secret key stored in non-volatile read only memory(ROM)and other dielectric,is extremely easy to attack through layout reverse engineering and micro-probing technique.These attack techniques greatly reduce the security level of the security chip.By capturing process deviations in the IC manufacturing process,physical unclonable function(PUF)circuit can generate random,unique and physical unclonable "chip fingerprint",which is very suitable for improving the security level of the security chip.Firstly,the research significance and status of the PUF circuit are analysised in the thesis.Secondly,the research is carried out from the aspects of structural design,chip implementation and fusion applications of PUF circuits.Finally,lightweight cryptographic protocols based on PUF circuit are proposed,and the fusion of PUF and advanced encryption standard(AES)is realized by FPGA.The research content of this thesis mainly includes the following parts:High-reliability PUF circuit design: A high-reliability and multi-port PUF with temperature and voltage compensation is proposed by using the random process deviation of current mirror structure through the research of temperature and voltage compensation technique.A high-reliability strong PUF circuit based on zero temperature coefficient(ZTC)point is proposed by studying the ZTC point of MOSFET and the current-mode strong PUF design technique.A highly reliable PUF circuit based on resistance-divider type DAC is proposed through the study of the integrated resistor deviation and differential compensation technique.All these proposed PUF are implemented by TSMC 65 nm process.Post-layout-simulation results show that the reliability of all the proposed PUFs is more than 97.8%(without applying any stability-enhancement techniques)in the range of voltage fluctuation of 10% and temperature variation of -40?120?,and it also has good randomness and uniqueness and other related characteristics.Low-power PUF circuit design: A low power and strong PUF based on the random process deviation of cascode current mirror is proposed through the research of current mirror structure and deviation-network multiplexing technique.Post-layout-simulation results show that it has very low power consumption.A low-power bi-stable PUF based on full NMOS PUF cell is proposed by studying the structure of bi-stable PUF cell and shared-head multiplexing technique.The PUF cell minimum feature size is 240F2 and the energy consumption is only 17.3f J/bit(@1.2V/50MHz).A low-power multi-port PUF based on MOSFET current-division deviation is proposed by studying the MOSFET current-division and multi-port PUF design technique,and the single port power consumption is only 0.32W(@1.2V/100MHz).All these proposed PUF are implemented by standard a 65 nm technology with custom-layout.Light-weight PUF chip implementation: Aiming at large area,high power consumption and low reliability of the CMOS structure bi-stable PUF circuit,a light-weight bi-stable PUF chip with stability-flag is designed based on 4T full NMOS PUF cell.It is implemented by TSMC 28 nm process.Measured results show that it not only has light-weight characteristic but also has function of stability-flag.In addition,a lightweight PUF chip based on the maximum-gain-point(MGP)deviation of the inverter is designed by studying the MGP deviation of the inverter and the lightweight PUF circuit design technique.The PUF cell is composed of high threshold transistors and current starved inverters.The entire chip is implemented by TSMC 65 nm process with full custom.Measured results show that it has extremely low-power consumption(13.8f J/bit @1.2V)and good randomness,uniqueness and reliability.PUF and cryptographic algorithm fusion: Aiming at the shortcomings of PUF-related cryptographic protocols in terms of scalability,database requirement and anti-attack,a scalable light-weight device authentication protocol based on PUF is proposed,which supports device and verifier mutual authentication and the certifier does not need to store a large number of CRPs.Then,a light-weight attestation protocol is constructed based on the proposed light-weight PUF circuit.The protocol is bound to the hardware features and can effectively defend against emulation attacks and physical attacks.Finally,an AES algorithm based on SRAM-PUF is proposed by using the unique attributes of SRAM initial-value and AES.It has hardware recognition attribute and is implemented by FPGA to verify its performance.This research can effectively expand the design concept of the novel PUF circuit and improve the overall performance of the PUF circuit.It also provides theoretical basis and method guidance for the VLSI design of the security-chip oriented PUF circuit,and points out the direction for the security chip to defend against physical attacks.