The Design And Implementation Of Multi-Channel CPRI Test System Based On FPGA

In recent years,with the development of mobile communications,5G related technical indicators are also gradually studied and perfected.In the future 5G network,in order to realize the high-speed access of the network,the antenna terminal will adopt Massive MIMO array.In this case,if the data transmission between the BBU(Building Baseband Unit)and the RRU(Radio Remote Unit)still uses the past single CPRI(Common Public Radio Interface)interface,the demand for huge data volume and transmission rate can not be satisfied.Based on this,the multi-channel CPRI interface is used in this paper.The BBU and RRU simulated by FPGA are connected through optical fiber,and the data transmission of the base station is simulated as a whole to meet the future demand.Based on the FPGA(Field-Programmable Gate Array),GTX(Gigabit Transceiver),CPRI protocol and other equipment and interface protocols,this paper designs a BER test scheme to simulate the data transmission of base station.Firstly,this paper selects the appropriate development board and chip,and for the BBU-side transmitter in the base station,selects the incremental and pseudo-random signal to be the source data of the BBU side.Then contrary to the CPRI group frame module,the GTX sending module and the clock generation module,the design and overall hardware simulation and debugging are carried out.This paper verifies the possibility of the implementation of the CPRI transmitter at the 9.8 Gbps line rate and ensures that the clock accuracy is controlled within a reasonable jitter range.Secondly,for the RRU-side transmitter in the base station,contrary to the GTX reception module,the CPRI solution frame module,and the BER calculation and transmission module,the design and overall hardware simulation and debugging are carried out.In this paper,a hyper-frame synchronization and slide synchronization are performed at the receiving terminal and the output BER values are passed to PC-side software written in Visual Basic language,so that the data can be analyzed and displayed.Finally,the simulation of the effect of clock jitter on the transmitter antenna in the real environment is carried out,and the method of eliminating the multi-channel jitter is proposed after analyzing the simulation results.Using Verilog hardware description language,this paper simulates the Massive MIMO data stream of 2 channels 16×16 architecture through FPGA,and establishes the multi-channel CPRI interface of sender and receiver,and use the optic fibre to realize the mutual interconnection between them,thus imitate the data transmission between BBU and RRU.By analyzing the simulation results of each module and the display data of PC,it shows that the whole project achieves the expected design requirement and verifies the correctness of the scheme,which has some reference significance at the present stage.