Research And Design Of CPRI Interface In Distributed Dase Dtation

Separating the base band processing unit(also known as wireless device controller, REC) and radio frequency processing unit(also known as wireless devices, RE) in conventional mobile communication base station, placed in the center of the room and the distal pole respectively, transferring data via optical fiber or cable connection to, which creates a distributed base station. It is highly pro-gaze in modern station building for quick construction of the base station, low cost, flexible networking, wide coverage, and high-capacity. In order to solve and norm fiber(or cable) data transmitting between REC and RE, Common Public Radio Interface Alliance proposed CPRI protocol specification, so through the CPRI interface communication connection between REC and RE can be achieved.This paper introduces the Universal Mobile Telecommunications System(UMTS), further analyzes the CPRI protocol specification, including the protocol data structure, the sub-channel, the boot process, data frames into solution, hyper frame synchronization. It describes the internal structure of FPGA and FPGA-based digital design process. In this paper, I achieve CPRI interface by useing FPGA as the main chip.Base on the analysis of protocol specification, CPRI is divided into physical transport layer and the data link layer. Wherein the physical transport layer is responsible for sending and receiving by SerDes module integrated in the FPGA, which sends to optical module(or receive) the data and completes the string 8b / 10 b encoding and decoding, and data(and the parallel-serial) conversion, since the 8b / 10 b encoding and decoding on transmission areas important meaning, this paper analyzes the codec principle and FPGA-based design codec module, shows waveform simulation map and RTL circuit diagram; the data link layer implemented by the FPGA, contain super frame synchronization warning module, a de-framing module, line rate negotiation module, this paper FPGA-based designs and implements the respective module and shows the simulation waveforms and RTL circuit diagram, they are full-featured, reliable performance.In order to verify the design of CPRI interfaces, a almost whole environment verification program is proposed, simulation waveform diagram illustrates more line rate also has a warning signal and other status indication and operators to manage maintenance data interface than the completion of the basic data transfer capabilities.Finally, together with optical modules and fiber for the design CPRI interface test board, waveform diagram grabbed by ChipScope clearly show a correct data transmission achievement.