VLSI Design Of Massive Mimo Detection Algorithm For 5G System

With the coming of the 5G era,Massive MIMO has become a new core technology.In a Massive MIMO system with numerous antennas,the complexity of the receiver detection algorithm becomes the bottleneck of the technology.So,there are huge implications to find a better detection algorithm to improve the performance of Massive MIMO.At the same time,the hardware realm ability of 5G technologies is a key part.In summary,this thesis focuses on the study of Massive MIMO detection algorithms in the field of wireless communications.For hard-decision MIMO systems and soft-output MIMO systems,select a classic detection algorithm to optimize and complete its hardware circuit design.The main contribution is as follows:1.MMSE detection algorithm study and its hardware architecture designThe minimum mean square error(MMSE)detection algorithm has received extensive attentions as one of the most classic detection algorithm in MIMO.There are some defects such as high hardware complexity and large delays when the existing architecture is used in Massive MIMO.This thesis studies the traditional MMSE linear detection algorithm and completes the hardware circuit optimization design.Firstly,the hardware implementation complexity of the traditional MMSE detection algorithm is transformed from the complex matrix inverse to the complex matrix QR decomposition by the way of formula transformation.The hardware design of this part is completed by MGS-QR method.Uses newton iterative method to calculate the inverse square root.The whole architecture is optimized in the pipelined design way to save the calculation cycles and reduce latency.Experimental results show that compared with other works,the computation cycle of MMSE detection algorithm is reduced by 51.54%,and the detection latency is reduced by 52.07%.2.MCMC detection algorithm study and its hardware architecture designIn massive soft-output MIMO systems,the complexity of Markov Chain Monte Carlo(MCMC)algorithm is linear with the number of iterations,while it can achieve near-optimal detection performance.It is considered as one of the most promising detection algorithms.This thesis focusing on the optimization of the new MCMC detection and completes its hardware circuit design.First,according to the characteristics of the data before and after the symbol mapping,the MCMC algorithm is optimized at formula level.Based on this,the hardware circuit corresponding to the algorithm is designed.Experimental results show that compared with the pre-optimization circuit,the proposed architecture increases the detection throughput greatly at the expense of increasing the limited area.The area utilization rate can be increased by up to 74.29%.In this design,the circuit area utilization increases with the increase of the modulation order,which can meet the detection requirements of a large multi-modulation system of a large antenna in the future.