Reasearch On Low-latency And Low Consumption CORDIC Algorithm And Architecture

Modern digital system are inseparable from the calculation of transcendental functions,and with the development of society and technology,people's requirement on the calculation speed of the system have become higher and higher,in general the calculation of transcendental functions cost a lot of time and a large amount of hardware resources,but the design of CORDIC algorithm is very clever which breaks down the complex operations into a series of addition and shift operations.With the development of the technology of LSI,CORDIC algorithm becomes more and more important,because it is very easy to implement with the modern hardware circuit technology which reduce the complexity of system design greatly.Currently many algorithms are not taking into account the design specifications of speed,area and power-consumption,how to guarantee the balance of speed,area and power-consumption is the key to research this algorithm.The thesis surveys the recent research on the CORDIC algorithm design,design and modify CORDIC algorithm against the limitations of conventional CORDIC algorithm,resolve the restriction among speed,area and power-consumption successfully.The modified algorithm uses shift operations instead of the lookup table to reduce the time of searching table which improves the speed,it also help to reduce the area.The modified algorithm removes some unnecessary iterations to reduce pipeline stages which also improves the speed.The two algorithms are implemented in Altera Corporation Cyclone series chip EP4CGX22CF19C6,the experimental results show that:this algorithm save 34.84%resources than conventional algorithm,and the maximum operating frequency increases about 11.28%,and it cost less about six clock cycles of delay on the different frequency,and the power consumption on different frequency decline about 5.54%at least,and the more the frequency improves,the more the power consumption declines.