Design Of SEU Hardened SRAM Cell And 512Mbit Memory

In space applications,the volume and energy of spacecraft and artificial satellites are limited,and integrated circuit chips are widely used for their small size,strong functions,and light weight.In the space environment,the chip will be impacted by a variety of high-energy particles and make mistakes,thereby causing hidden dangers to the normal operation of aerospace equipment.As an important part of cache,SRAM plays a decisive role in a chip.SEU is easy to change the storage content when impacted by high-energy particles,so SRAM memory needs to be strengthened against SEU.This article uses cadence spectre software and uses SMIC 65 nm process to do research of a high-performance SEU hardened SRAM cell-HP10 T cell,and performs a design of memory based on this memory cell.In this paper,firstly,the possible radiation effects of SRAM memory in space environment operation are described,and the necessity of SEU hardened design of SRAM memory is analyzed.Then,the method of SEU hardened of SRAM memory is introduced,and choose circuit-level hardening as the main way to do the research of memory cell.Nextly,the mechanism of SEU of standard 6T SRAM cell is analyzed,combined with the RHPD-12 T cell,the research of the hardened memory cell and its simulation verification and comparative analysis are carried out.Finally,the structural design and timing design of 512 Mbit SRAM memory are performed.After the above progresses are completed,the peripheral circuit design of the SRAM memory is carried out,and the integration and functional simulation verification of the overall circuit are carried out,which shows that it can correctly complete memory operations.Then,the layout design of the memory cell and the peripheral circuit are designed,and the integration and improvement of the SRAM layout are carried out.Finally,the parasitic parameters of the layout is exported,and post-layout simulation is performed to verify the correctness of the design.The result of post-layout simulation shows that the memory can work normally under the clock with a period of 10 ns.