Harden Design And Verification Of PowerPC Processor

It is well known that there are a large number of radiating particles in the working environment of spacecraft.The chip is the core of the aerospace computer.In the high-altitude radiation environment,the radiation generated by the high-energy particles will cause the single-event upset(SEU)of the memory which occupies most of the chip.The SEU will give rise to the error inversion of the on-chip memory cell,thus affects the normal operation of the system.The X_DSP processor is a multi-core SoC used in the aerospace industry.One of its cores,the PowerPC460,does not have the reinforcement capability.This paper focuses on the original storage mechanism of the PowerPC460 processor core of X_DSP processor.The error correction and reinforced algorithm are analyzed in detail to realize the EDAC harden design of the PowerPC460 processor core,which could ensure the safety and reliability of the X_DSP in the radiation space.This paper includes following aspects: 1.The structure of the X_DSP processor and the original structure of the PowerPC460 on-chip memory are analyzed.By studying the reinforced requirement,the specific reinforced scheme is designed.2.The RTL-level codes based on BCH DEC-TED encoding is designed,which includes the acquisition of the check matrix,the check digit and the generation of the syndrome,etc.Hence,the one bit or two bits error of information data can be corrected.The three-digit error can be detected,and the error location is calculated.By using the scripting language python,a DEC-TED parameter template based on BCH code is designed,including the DEC-TED coding parameterization template and the decoding parameterization template.What’s more,the template of the RTL code is obtained,in which the corresponding BCH DEC-TED codes can be quickly generated according to the demand parameters.3.For the reinforcement of PowerPC460,a series of EDAC hardening control registers are designed.By using these hardening control registers: the background refreshing mechanism of EDAC,two different error correction mechanisms,background buffering mechanism,etc.,are designed for the memory of PowerPC460.The EDAC harden design for PowerPC460 which has two different error correction capabilities is finally realized by designing these reinforced mechanisms.4.The SEC-DED codes algorithm based on Hsiao code,the BCH DEC-TED codes algorithm module designed in this paper and the function points of the EDAC harden design are verified.Then the verification of PowerPC460 in single core level,system level and FPGA are accomplished.Finally,the harden design of two different error correction capabilities is evaluated.According to the evaluation results,a suitable reinforcement scheme is selected for the harden design of the X_DSP processor.