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Research And Development Of Decoding System For Resolver Transformer

Posted on:2020-08-17Degree:MasterType:Thesis
Country:ChinaCandidate:C ChenFull Text:PDF
GTID:2392330602951918Subject:Engineering
Abstract/Summary:PDF Full Text Request
In this thesis,based on the research of the resolver position calculation system in the pod,and the radar.Two resolver digital converter systems are designed for the signal-channel resolver and the dual-channer resolver,correspondingly.Both designs implement the overall design,circuit design,FPGA software development and the experimental test of the decoding system.The error correction encoding method in the design for the dual channel resolver is also solved.Additionaly,the design of the CORDIC decoding algorithm is completed based on FPGA,and the algorithm is implemented.The feasibility of this algorithm is verified by the simulation carried by Modelsim.The main completed contents are as follows: 1.The overall scheme of the single-channel resolver decoding system is proposed based on the characteristics of the single-channel resolver used in the radar servo system.The core device selection and circuit design of the system are completed,and the feasibility of the circuit design is verified by Multisim.Then the FPGA software design is modularized,and the system software design is verified by the simulation carried by Modelsim.Lastly,the experimental test shows that the single-channel resolver decoding system meets its functinal requirements.2.The overall scheme of the dual-channel resolver decoding system is determined based on the characteristics of the resolver used in the radar servo system.The error correction problem existing in the dual channel decoding system is analyzed and the solvetion is given.The circuit design and device selection of the system are completed,and the circuit design is verified by the simulation conducted by Multisim.Then the FPGA software is designed with top-down method,and the function simulation of each sub-module is carried out by Modelsim software.Lastly,the experimental test verifes the feasibility of the design by showing that the dual-channel resolver decoding system meets its functinal requirements.3.The solution method of replacing the dedicated decoding circuit with CORDIC algorithm is designed.Firstly,the principle and the theory of CORDIC is explained.Then the rotating mode and the vector mode are analyzed amply.Lastly,the software implementation process of CORDIC was designed by FPGA and verified by Modelsim.The feasibility of the design is attested.
Keywords/Search Tags:FPGA, CORDIC, Error correction encoding, Resolver digital converter system
PDF Full Text Request
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