Research On Hardware Implementation Method Of LDPC Decoder Based On FPGA

In the application of telemetry remote control,digital communication system is an indispensable and important part.With the increasing demand for deep space exploration,the communication distance of telemetry and remote control is enlarged dramatically,and the amount of data transmitted between flight vehicle and the ground base is also increasing;therefore,the technical requirements for digital communication system has been increased continuously.Due to the long communication distance of the telemetry remote control system and the severe signal attenuation,the communication quality is degraded.In order to guarantee the efficient and reliable transmission of data,a high-performance error correction code is needed as the channel coding.Low-density Parity-Check Codes（LDPC）has been applied to various digital communication system standards due to its performance that is close to shannon’s limits.In practical application,the decoder is the core part of the whole system,and the decoder needs a lot of calculation in the decoding process.In order to guarantee the real-time performance of decoding and improve the decoding rate,it is necessary to design a feasible hardware implementation scheme of decoding algorithm.This paper is to study the FPGA implementation method of LDPC code decoder whose code length is 1408 and information bit length is 1024 under CCSDS standard.In order to implement the（1408,1024）LDPC code decoder under CCSDS standard,this paper firstly studies the basic principle and specific form of CCSDS standard LDPC code,and then compares and studies three classical Belief Propagation decoding algorithms.By combining the layered decoding idea with the minimum sum decoding algorithm,this paper proposes a layered minimum sum decoding algorithm which is suitable for hardware implementation.We use MATLAB to simulate the layered minimum and decoding algorithm,and analyze the error correction performance of the algorithm.Then,in order to determine the specific decoding parameters in the hardware implementation of the decoding algorithm,we use MATLAB to conduct multiple sets of simulation experiments on the maximum number of iterations and quantization digits,and analyze the impact of the above two parameters on the decoding performance and determine the decoding parameters in the final decoder implementation.This paper compares the three schemes of serial architecture,full parallel architecture and partial parallel architecture for the FPGA implementation of LDPC decoder.Based on this,the overall architecture of the layered partial parallel decoder is given by combining the layered minimum sum decoding algorithm with the partial parallel architecture.Then we designe each subunit of the decoder,and complete the FPGA implementation of（1408,1024）LDPC code decoder successively.Finally,we build a decoder test system to test and analyze the performance of the decoder by using the NI PXIe device and the LabVIEW FPGA development environment.Experiment results show that,the maximum clock operating frequency of the LDPC decoder designed in this paper is 108MHz.When the signal-to-noise ratio is3dB,the bit error rate is10^-6 orders and the throughput rate of this decoder is170Mbps.