Research On LDPC Decoding Algorithms And Decoders Design In Space Communications

In recent years,with the rapid development of China aerospace industry,the complexity of space missions is increasing and the accuracy of data generated by payloads in spacecraft is improving,which makes the amount of data transmission between ground and spacecraft increase rapidly.A powerful error correction code is needed to guarantee the secure transmission of data.Low-Density Parity-Check(LDPC)code,as a linear packet code close to the Shannon limit,has been widely used in various digital communication standards in recent years,such as 5G New Radio,802.11 n.In the field of space communication,Consultative Committee for Space Data Systems(CCSDS)and European Telecommunications Standards Institute(ETSI)have also designed suitable LDPC codes for different data transmission environments,respectively.In the decoding of LDPC codes,the merit of the decoding algorithms largely affects the performance of LDPC codes,and the design of the decoders are related to the overall efficiency of the communication system.In this paper,we conducted an in-depth study on decoding algorithms and decoders design,and the main research work are as follows.(1)The development of current LDPC decoding algorithms are fully investigated,and the differences in complexity,BER performance and convergence speed of various decoding strategies are analyzed and compared.Two improved scheduling-based decoding algorithms are proposed after an in-depth analysis of the message propagation mechanism in the iterative decoding strategy.The first one reorganizes the parity-check array(PCM)according to a priori ranking criterion,which based on the characteristics that the PCM of irregular LDPC codes have different row weights and column weights.And then the reorganized PCM is used for decoding.The second method measures the confidence of the decoding messages by introducing the residuals,and gives priority to the decoding layer with higher confidence.The complexity analysis and performance simulation show that the two decoding algorithms proposed in this paper have lower bit error rate(BER)and faster convergence speed compared with the traditional decoding algorithms.(2)Traditionally,implementing high-speed LDPC decoders on field programmable gate arrays(FPGAs)requires manual tuning using hardware description languages(HDLs)such as VHDL,which requires developers to understand the details of the hardware,requires a lot of efforts to continuously do simulations and verifications during the development process,and makes it difficult to implement parametric designs.In this paper,an efficient LDPC decoder architecture is designed using the High-Level Synthesis(HLS)tool,i.e.Vivado HLS,which takes advantage of the software development language to achieve a parametric design,so that decoders with different codes can be implemented in a very short time.The decoders have a throughput of 150-300 Mbps with a low hardware resource occupation,which can meet the data transmission requirements in current space communication and have a high practical value.