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Design Of Low-level Control System Of Superconducting Accelerator Based On FPGA

Posted on:2019-05-18Degree:MasterType:Thesis
Country:ChinaCandidate:P ZhaoFull Text:PDF
GTID:2382330563495225Subject:Mechanical engineering
Abstract/Summary:PDF Full Text Request
Low-level control system,abbreviated as LLRFCSS(Low Level Radiation Frequency Control System),is mainly used in accelerators fields such as superconducting accelerators or superconducting acceleration cabins.Its main function is to stabilize the frequency of high-frequency cavities,the amplitude and phase of high-frequency signals to make the superconducting cavity work stably for a long period of time,and its performance index has a great influence on beam quality.In recent years,low-level technology has gradually evolved from analog low-level control technology to digital IQ technology,which greatly improves the performance of low-level systems,and places high requirements on the design of hardware circuit for low-level systems.The project uses a high-performance FPGA as the main control chip,an efficient ADC+FPGA+DAC data processing architecture with high-performance digital signal processing demodulation circuit,the main control board integrated standard Ethernet high-speed interface,high-speed USB interface to build high-speed signal vector IQ Demodulation,large-capacity storage,and complex low-level control systems that can communicate with the host computer in real time.The main contents of the thesis research include:1.The functional requirements of each module of the low-level controller hardware system are analyzed.By the introduction of the basic structure of the low-level control system,the overall hardware architecture of the low-level control system and the design of the hardware circuit are determined.2.In the design of the low-level controller hardware system,the hardware implementation of the high-speed signal acquisition specifically includes the hardware design of the system sampling clock circuit and the sampling circuit;the hardware implementation of the high-speed digital signal processing module specifically includes the selection of the FPGA chip,FPGA chip pin resource allocation and onboard data cache hardware circuit design;hardware implementation of the data interface module specifically includes the Ethernet data interface,high-speed USB bus interface,hardware circuit design,etc.Finally,introduced the hardware circuit design of the digital signal recovery part.3.For the design of the power supply module,the power supply types and power consumption requirements of the entire low level controller hardware system are statistically analyzed,and a power supply circuit that meets the requirements is designed.4.Finally,we tested the power supply module and the hardware circuit design part of the FPGA development board of the designed low-level system.The test results show that the hardware circuit design of this paper is correct and can meet the requirements of the low-level control system project,thus verifying the correctness of the design scheme of this paper.
Keywords/Search Tags:field programmable gate array, low-level control system, digital IQ, circuit design, superconducting accelerator
PDF Full Text Request
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