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Design And Implementation Of Low Voltage Differential Linear Regulator With High Power Supply Rejection Ratio

Posted on:2019-01-28Degree:MasterType:Thesis
Country:ChinaCandidate:Z Q GuanFull Text:PDF
GTID:2382330545486615Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
The power management chip is widely used in the portable equipment,which influences the performance of the whole circuit driectly.Low dropout regulator(LDO)has gained much attention for its advantages in all kinds of field,and its low cost.Therefore,it’s of great significance to study LDO.This paper fully analyzed the development trend of LDO and the domestic and foreign quotations lately.The broad application prospect of LDO was also proposed.The LDO designed in this paper is a classic loop structure,the principle of LDO and the process of derivation of PSR are introduced in detail.At the same time,four methods to improve the PSR of LDO,such as improving the band gap datum,improving the loop gain and so on,are given.Then the principles of three band gap structures are compared under the 0.35 m process library.It can be seen that the improved current sum type bandgap circuit with the pre voltage negative feedback structure has the best PSRR performance,and the PSRR in the 100 Hz frequency range can reach 108 d B,which is much higher than that of the general band gap circuit.The error amplifier of this paper adopts a common cascade two stage amplifier structure.The low frequency gain is 92 d B,the phase margin is 74 degrees,the common mode rejection ratio is 82 d B,and the power supply rejection ratio is 90 d B.The PMOS element is used as a power tube with a differential pressure of 0.2V.In the end,we use the improved filter circuit to improve the LDO circuit,and use the way of increasing impedance on the path to reduce the sensitivity of the LDO output terminal to the power supply voltage,so as to improve its PSR.Before the improvement,the PSR can reach 89 d B in the 100 Hz frequency,and the PSR of the improved LDO reaches 106 d B.The loop gain is improved LDO up to 113 d B,phase margin of 53 d B,a range of 2.7 V-5 V,load adjustment rate is 2.3%,the linear adjustment rate of 0.04%,the fastest time for 30 s,the static current of 1.4 m A,the maximum current efficiency is 98.6%,the temperature drift coefficient is 13.41 ppm/℃.
Keywords/Search Tags:LDO, PSR, power management chip, bandgap reference, error amplifier
PDF Full Text Request
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