| In the past decade,with the progress of science and technology,more and more social production activities have begun to develop in the direction of digital intelligence.The emergence and popularization of smart phones and other devices have greatly facilitated human life and work.In this era,there is no doubt that intelligence has become the general trend.With the rapid development of wireless communication,intelligent products,image processing technology and other technologies,the demand for matching power management chips is also increasing.Among them,DC-DC chip has become a hot spot in the current market due to its small size,high accuracy,low power consumption and other advantages,and has a broad market prospect.In this paper,the three topologies of DC-DC converter chip are deeply studied,and the working mode and control mode of Buck DC-DC converter are analyzed.The control principle of PWM pulse width modulation and PFM pulse frequency modulation,which are commonly used in the chip design,are described.The advantages and disadvantages of voltage feedback and current feedback are analyzed,which provides a theoretical basis for the chip circuit design.According to the theoretical guidance and the requirements of chip performance parameters,this paper designs a dual channel PWM Current Mode Synchronous Buck DC-DC chip for DDR memory.The chip has two voltage outputs.The phase difference of the two output voltages can be controlled by the pin voltage to reduce the output voltage ripple.The voltage tracking between channels can be realized by dividing the voltage of peripheral resistance.The full working voltage input range is 5～15V,the output voltage range is 0.9～5.5V,and the working frequency is synchronized at 300 k Hz under PWM.Combined with the circuit as a whole,the improvement of output voltage accuracy and the reduction of static power consumption are studied,and the solutions to improve the related performance are analyzed.In order to realize the overall function of the circuit,the module circuit including bandgap reference circuit,error amplifier,comparator and so on is designed in the circuit design chapter,and the performance of the module circuit and the overall circuit is simulated and verified respectively.The multiplexed five transistor operational transconductance amplifier structure with a hospital reference circuit in this design achieves a large power rejection ratio without additional use of complex operational amplifier circuits.Miller compensation is applied to the error amplifier,and the left half plane zero is used to offset the influence of the secondary pole in the bipolar circuit,so as to ensure the stability of the circuit.In addition,the internal circuit also includes soft start circuit,undervoltage latch circuit,drive circuit and so on,which ensures the safe and reliable operation of the chip.The circuit uses 0.35 μm BCD process,and uses Cadence software to complete the circuit schematic construction and simulation verification,and completes the layout design of the overall circuit.Finally,this paper analyzes the test results of some parameters after tape-out,and concludes that the static current of this chip is less than3 mA,and the reference accuracy reaches 0.3%,which has the characteristics of high accuracy and low power consumption,and meets the design requirements.The deficiencies of the project design process are summarized,and the design experience is accumulated.It is verified that each index of the chip meets the expected index,and the design task is basically completed. |
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