| In the fields of cloud computing and big data,precise data collection devices are required to process and analyze the data obtained by sensors.As a data acquisition chip in cloud computing and large data applications,MCU may not obtain stable voltage due to power voltage fluctuation,external noise and other factors,which may cause its normal operation to be disturbed or abnormal,and cannot collect correct data.Therefore,stable and reliable power supply is needed to ensure the normal operation of the system.Low-voltage differential linear regulator(LDO)is a solution to provide a stable power supply.It has the characteristics of small pressure difference,small ripple,low noise and small temperature drift.It can provide a clean and stable power supply for MCU,and ensure the stability and accuracy of the whole system.Using 0.18μm CMOS process,this article designs and implements a novel high-precision LDO.It consists of a bandgap reference source,an error amplifier,a power stage circuit,and a feedback resistor network.It adds a digital tuning circuit on the basis of the traditional first-order bandgap reference to reduce the impact of temperature and process deviation,improve the accuracy of the bandgap module,and indirectly improve the accuracy of LDO;A special common gate stage structure is used at the second stage of the error amplifier to push the poles inside the amplifier away from the origin,ensuring the stability of the LDO system.At the same time,the high gain of the common gate amplifier also improves the power suppression(PSR)in the low frequency range;In order to obtain a wider range of programmable output voltage,a 4-digit digital signal is used to control the feedback resistor ladder,and different output voltages are obtained by adjusting the resistance value.Under simulation conditions with a process angle of TT and a temperature of 27℃,the adjustable output voltage of LDO ranges from1.361V to 1.860 V;The linear adjustment rate is 50.3μV/V when the operating range of the power supply is from 2.3 V to 3.3 V;When the load changes from 0 to 20 m A,the load adjustment rate is 9.6μV/m A;Monte Carlo simulation results show that the variance is 3.8×10-4 V2;The power supply rejection of the LDO in low frequency under a load current of 20m A is-97 d B.The phase margin of the circuit is always greater than 66°at different process angles.The chip is tested by stream chip.The test results show that the output voltage range is stable from 1.8063 V to 1.8082 V,and the output error is less than 0.2%.The LDO power suppression test result at 100 Hz is-78 d B,which meets the practical application requirements. |