Design And Implementation Of Key Modules For Power Battery Management Chip In New Energy Automobile

New energy automobile is regarded as one of the best methods to solve the problem,such as energy sources,environmental protection and safe driving in auto industry.It has received much more attention than before by governments and enterprises around the world.One of the most significant automobile electronic chips in new energy automobile is power battery management chip,which can detect the voltage of battery cells in series and be used by stacking.Study in this field is urgently needed in our country.This paper analysis the system structure of power battery management chip and designs three key modules,including high precision bandgap voltage reference,cascading communication and 10 MHz clock under the ASMC 0.5?m 60 V BCD process,based on the test results of other two key cuicirts,power management on chip and battery voltage acquisition front-end(MUX+ADC).First,a high precision bandgap voltage reference is given.By partition of temperature range(-40? to 125?),basic bandgap core is compensated by different constant current and PTAT current to get a 2.42ppm/? temperature coefficient.This circuit works under 5V supply voltage and gives 3V output.Load current is up to 20 mA.Next is the design of cascading communication.Transmitting circuit applies LVDS mode to lower the noise interference with output of 3.2V in high,1.8V in low and 2.5V in middle.Differential signal surmounts a potential barrier up to 40 V by isolation transformer and is transmitted by twisted pair and finally received by a comparator.The minimum pulse width that can be transmitted is 100 nS with 72.45 nS delay time.Finally,a 10 MHz clock focused on the temperature and process compensation is designed.Five modules are included in this part: temperature and process compensation,the bias module,the differential input/output delay module and the comparator module.Output frequency is fluctuated around 10 MHz with ±20% error.Pre-layout simulation and layout design have been done for all modules above.Bandgap voltage reference is running on the process line now.Interface and 10 MHz clock are prepared to be submitted for tape-out.