Design Of A Configurable Low Power Cyclic ADC For MAPS

Exploring the basic composition of matter and the interaction between particles has always been at the forefront of research in high-energy physics.The pixel sensor detector and its special integrated circuit play an important role in detecting particles.The active pixel detector MAPS(Monolithic Active Pixel Sensor),as one of the pixel detectors,is extremely important for detecting high-energy particles in the universe.For the process of converting analog to digital in the detection of high-energy particles by MAPS,a suitable on-chip ADC needs to be adopted to meet the requirements of its accuracy,power consumption,and area.Cyclic ADC adapts to the requirements of MAPS pixel detectors for column ADCs due to its low power consumption and small area.This article has designed a precision configurable Cyclic ADC based on MAPS,which adopts digital-analog hybrid design,and its precision can be configured into different values according to different applications.The maximum sampling rate corresponding to each accuracy is different.The maximum sampling rate of 4 bits is10 MHz,the maximum sampling rate of 5 bits is 8MHz,the maximum sampling rate of 6 bits is 6.66 MHz,the maximum sampling rate of 7 bits is 5.71 MHz,and the maximum sampling rate of 8 bits is 8 5MHz.Users can choose different precision modes and different sampling rate modes according to their own needs.In contrast,the configurable precision design meets the needs of different applications to a greater extent than a single precision ADC.This ADC uses a special sample-and-hold structure that combines sampling and holding.Compared with the sample-and-hold structure of other Cyclic ADCs,this saves one cycle in time and improves the efficiency of sampling and calculation.In MDAC,the capacitor is connected to the design so that this structure can effectively prevent the accumulation of errors in the output result due to the accumulation of charge caused by the continuous sampling and calculation of the same capacitor.The 1.5-bit sub-ADC used in it and the subsequent digital correction method effectively eliminate the offset error generated by the comparator.The height of this ADC layout does not exceed 100?m,and the width does not exceed 300?m.The analog part is powered by 3.3V and the power consumption is 4.98 m W.The digital part is powered by a 1.5V power supply and the power consumption is 38.24?W.The input dynamic range is 1V,and the 8-bit mode ENOB is configured to 8.07 bits.The design of this Cyclic ADC meets the requirements of MAPS fordigital-to-analog conversion,and can be extended to other similar applications that require digital-to-analog conversion.Its small power consumption,small area,and configurable advantages make this design widely used.