Research And Implementation Of Cryogenic Analog-to-Digital Converter For Silicon-based Quantum Computers

Quantum computing is based on quantum bits(qubits)and enables parallel computing,presenting new opportunities and challenges for network security based on existing cryptographic algorithms.To tackle the challenge of breaking large-scale quantum bits,cryogenic control circuits for quantum chips have received widespread attention and research.Currently,the main focus of research on cryogenic CMOS technology is on achieving high-quality microwave pulse excitation,but there is relatively little work on achieving high fidelity quantum state readout.This work faces many technical challenges,including CMOS characteristic offsets at cryogenic temperatures,the establishment of compact models for correlation,cryogenic CMOS flicker noise and mismatch amplification,and limitations on the power of cooling machines.This dissertation focuses on the measurement and readout requirements of silicon-based quantum computers,and conducts research on the design and implementation of cryogenic analog-to-digital converter circuits.The main content includes:1.This dissertation introduces the background and progress of cryogenic measurement and control circuits,and combines with the development trend of various architectures of analog-to-digital converters in the current stage.It introduces the gradually gained attention and development of the mixed architecture of successive approximation type and noise shaping successive approximation type.Then,the dissertation briefly introduces the basics and principles of analog-to-digital converters,analyzes the characteristics of noise shaping and oversampling technology,and the non-ideal factors of key circuits.2.Following the bottom-up principle,this dissertation provides a detailed analysis of the characteristics of 180 nm CMOS technology at cryogenic temperatures,including increased mobility,elevated threshold voltage,steeper subthreshold swing,and kink effects.Based on the BSIM3V3 compact model at 4.2 K,the dissertation also provides a detailed introduction to the operating characteristics of cryogenic inverter、cryogenic ring oscillator and cryogenic D flip-flop circuits.3.This dissertation presents the design of a cryogenic 8-bit 32 MS/s SAR ADC with bottom-plate sampling.A high linearity bootstrap switch is designed using a bottomplate sampling approach,and a charge pump voltage boosting switch is used for the top-plate switch design to compensate for the long Vcm voltage transfer time caused by the increased threshold voltage at cryogenic temperatures.The CDAC module uses a Split capacitor switching sequence to save the bottom-plate Vcm reference voltage and avoid the effects of the threshold voltage.The SAR logic circuit uses dynamic logic to ensure the speed of digital code locking and further reduce power consumption.The simulation results show that the differential non-linearity(DNL)is between-0.15 LSB and 0.2 LSB,the integral non-linearity(INL)is between-0.2 LSB and 1 LSB,the signalto-noise-and-distortion ratio(SNDR)is 47 dB at the input Nyquist frequency,and the spurious-free dynamic range(SFDR)is 61 dB.The overall power consumption is 2.5 mW.4.This dissertation presents the design of a cryogecic 2nd order passive NS-SAR ADC.Based on a 10-bit Vcm switch switching sequence SAR ADC,the design incorporates a charge-sharing passive loop integrator for low power consumption and high robustness,while avoiding the problem of cryogenic mismatch caused by too many active circuit modules.The design realizes a 3-input improved Elzakker two-stage dynamic comparator,which reduces the comparator clock load and achieves amplification and summation of residual voltage and integration voltage.The simulation results show that the peak SNDR is 83.8 dB and the SFDR is 86.9 dB for a 46.8 kHz sine wave input.Compared to SAR ADCs without noise shaping,the SNR is improved by approximately 22 dB,and the overall power consumption is only 585 μW.The innovations in this dissertation include:1.Starting from the cryogenic model at the bottom level,the circuit characteristics of cryogenic inverters,cryogenic ring oscillators,and other circuits were studied in detail.The static and dynamic circuit characteristics were studied,and the inverter switch threshold VM and transfer characteristics,ring oscillator propagation delay characteristics,static power consumption,dynamic power consumption,etc.were explained in detail.2.Using the "model first,design later" approach,the impact of cryogenic circuit characteristics on the design was considered.Two low-power ADCs working at 4.2 K were designed using the cryogenic compact model based on BSIM3V3.This has important implications for the implementation of measurement readout circuits for quantum computers.At the same time,the designed passive NS-SAR ADC is the first NS-SAR ADC to operate at 4.2 K.