Research Of IF Digital Receiver Based On FPGA

In recent years,the software defined radio is one of the widely concerned technology,which is based on digital signal processing and widely used in civil and military fields.The modern IF digital receiver is the key technology of software defined radio.With the development of microelectronics and semiconductor industry,a variety of chips have been developed,FPGA(Field Programmable Gate Array)has a good performance in performance,power consumption,flexibility and other aspects.Using FPGA for circuit design is the focus of current research,this design is based on FPGA.The research background and significance of IF digital receiver was introduced in the thesis.The present situation of the receiver was explained from both domestic and foreign aspects.The theory of receiver design was introduced,and the modulation and demodulation models of band-pass sampling theorem and DQPSK signal were emphasized.Quartus II software was selected as a software development platform.Verilog HDL language was selected as the development language.Modelsim software was selected to make functional simulation.MATLAB software was selected to simulate important modules.The important modules which make up the receiver are carrier synchronization,frequency offset estimation,bit synchronization module and so on.M-th power loop,Costas loop,polar Costas loop,decision feedback phase-locked loop was described in the thesis.The anti-noise performance of the different loops were simulated and compared,finally,polar Costas loop was selected to realize the carrier synchronization.The frequency offset estimation module can be combined with the carrier synchronization module to improve the loop performance.Several methods of frequency offset estimation were introduced,and the method of FFT frequency offset estimation was selected,this method was simulated and analyzed.The principle of bit synchronization and commonly used methods of implementation were described in the thesis,Gardner bit synchronization was selected finally.All parts of Gardner bit synchronization were described and simulated.MATLAB was used to simulate the receiving signal,then the various sub-modules were built and simulated.After the sub-modules simulation without errors,these modules were connected to the overall simulation.Finally,the entire project was compiled and downloaded to Altera's EP4CE10F17C8 N chip.Signal tap ? was used to view the internal signal,the hardware test chart was compared with functional simulation diagram of the whole system to verify the correctness of the receiver demodulation process.