Research On Fabrication And Performance Of Thin Film Transistor Based On Pentacene

Organic thin film transistors?OTFTs?have attracted considerable attention due to their advantages of low cost,good uniformity,large area fabrication,and ability to be fabricated on flexible substrates.In recent years,OTFT has been rapidly developed and has great potential for application in flat panel displays,sensors,and detectors.However,OTFTs still have problems such as low mobility,insufficient stability,and high driving voltage.In this paper,high dielectric constant oxide is selected as the gate insulator material to reduce the driving voltage of the thin film transistor.We have studied the effect of the gate insulator layer on the device performance and optimized the active layer structure to improve the performance of the thin film transistor.The specific works of this paper are as follows:1.We select the high dielectric constant zirconium oxide as the gate insulator layer and select pentacene as the active layer.We use PMMA to modify the gate insulator to improve the morphology of the zirconia insulator,reduce the trap density,which greatly increase the size of pentacene crystal grains and reduce the number of grain boundaries.So,the purpose of improving the transmission efficiency of the carrier and improving the device performance is achieved.On this basis,we further study the effect of gate insulator layer thickness on the device performance.The thickness of the gate insulator layer affects the dielectric properties and film morphology,and more importantly,it affects the size of the gate insulator layer capacitance.On the premise of good dielectric properties,we increase the capacitance of the insulator layer and increase the charge accumulation capacity of the conductive channel to obtain optimal device performance.The experiment results show that the thin film transistor device exhibits the best performance when the thickness of PMMA-modified zirconia insulator layer is 56nm.The device mobility is 0.335cm²/Vs,the current on/off ratio is 1.14×10⁴,the threshold voltage is-0.99V,and the subthreshold slope is 0.5V/dec.2.To optimize the structure of the active layer of thin-film transistor devices,we insert a layer of 1nm F₁₆CuPc in the middle of the pentacene and design it as a pentacene/F₁₆CuPc/pentacene sandwich structure to study the effect of the sandwich structure on the performance of thin-film transistor devices.The experiment results showthattheF₁₆CuPc/pentaceneheterojunctionstructureinthe pentacene/F₁₆CuPc/pentacene sandwich structure can effectively increase the number of free carriers and fill the carrier traps.On the other hand,this structure can effectively reduce the channel resistance,which can increase the conductivity of the conductive channel and improve the efficiency of charge carrier transport.Finally,the purpose of improving the performance of TFT is achieved.The TFT mobility of the device based on the pentacene/F₁₆CuPc/pentacene sandwich structure is 0.4cm²/Vs,the current on/off ratio is 1.25×10⁵,and the threshold voltage is-10V.