S Band Frequency Synthesis Technology

In modern electronic system frequency synthesizer is very important.The electromagnetic wave in S band is widely used in military,consumer electronics and satellite communication systems.The purity,switching speed and resolution of the frequency source have an important influence on all kinds of electronic systems.The design method of frequency synthesis has now experienced the development of three generation technology.In this paper a S band frequency synthesizer is designed.Firstly,the principle of digital direct frequency synthesis(DDS)and phase-locked frequency synthesis(PLL)is introduced,and the principle and model of spurious and noise generation in DDS are discussed.In view of the phenomenon of phase truncation in DDS,the approximate calculation formula of the maximum spurious component is given and verified with the tools of Matlab and other tools.Starting from a basic phase-locked loop model,the influence of PLL loop bandwidth on the performance of phase-locked loop is expounded,and the principle of fractional frequency in PLL is also introduced.In these theories,this paper designs a hybrid frequency synthesizer that uses DDS to drive PLL directly.A relatively large phase detection frequency is selected in the PLL,thus reducing the locking time.On the software part,this article designs a set of interface and graphical interface on the PC platform,which facilitates the test and development of the frequency synthesizer again.In this design,DDS module uses ADI AD9914 chip,DDS module design output frequency is 0-1GHz,frequency resolution is less than 0.6Hz,phase noise is superior to-80dBc@1kHz,and besides output point frequency,there are various output modes.In order to reduce the complexity of the system hardware,the DDS's built-in phase locked loop is used to provide the clock signal for itself.During the operation of the system,the DDS module is controlled by the host computer through FPGA,and the output frequency and output waveform of the DDS module can be changed at any time by the software interface.The most is the PLL module design,this paper designs an output frequency in PLL 3.1-3.3GHz circuit,PLL module driven by the DDS module,the output phase noise is better than-88dBc@10kHz,and the frequency step can be less than 10 Hz,the switching time of the frequency source system is less than 150 us.By using Modelsim to simulate the Verilog program in the software,the correctness and rationality of the internal module design of FPGA is verified.Finally,this paper designs a group of software interfaces on the PC platform,and uses the Qt Creator tool to design the graphical interface.