10G-based Deterministic Network Node Card Logic Design

In some emerging fields such as vehicle-mounted system,industry automation and the Internet of things,the demands of application for real time,determinacy and reliability have increased.In terms of compatibility and reliability,some specialised network solutions in the early time proposed the idea of time synchronization and time scheduling which didn't work well.In order to meet the increasing market demand,the TSN protocol cluster in the drafting stage standardizes traffic scheduling,time synchronization,traffic monitoring,and fault tolerance mechanisms.In the consideration of the expanding requirements of bandwidth,this article make a combination of 10 G Ethernet and deterministic network,aiming at increasing the bandwidth of deterministic networks as well as giving 10 G Ethernet real-time characteristics.This article compares IEEE 1588 with IEEE 802.1AS and find that 802.1AS is more compatible.Its synchronization algorithm is more concise and easy to implement.Besides,it is applicable to many types of networks.Therefore,this paper takes the 802.1AS time synchronization protocol as one of theoretical bases.In deterministic networks,the time-triggered traffic scheduling feature is one of the most valuable features.Based on time periods,the IEEE 802.1Qbv protocol uses a multi-queue transmission gate control method to define the enhanced traffic scheduling mechanism.This paper adds scheduling traffic queues to traditional Ethernet queue making traditional Ethernet compatible with deterministic networks and the design become more flexible.In the interaction of the node card and the CPU,this paper adopts PCIe-based DMA method,which not only satisfies the need of high-speed data transmission,but also provides a rich register interface to facilitate the dynamic configuration of the upper application.The most important design of the paper can be devided into two parts.One part is the 10 G Ethernet data path.This part implements the high-speed data transmission function from the bottom layer to the DMA logic.The other part is the synchronous auxiliary and traffic enhancement scheduling,which contributes to the time synchronization and implements enhanced traffic scheduling.The design of this article primarily relies on the FPGA hardware platform.Because it can decrease development time and make design flexible.After that,this article use Modelsim simulation tool to simulate every module's function.Then the data path was tested at the board level.It is found that the scheme can be controlled according to a predetermined cycle time to meet the design requirements.The node card designed in this paper has a pretty high bandwidth,and its design of synchronous auxiliary and traffic scheduling also can be used in other bandwidth deterministic Ethernet.