Design And Implementation Of UFMC Baseband System Based On FPGA

Nowadays,Orthogonal Frequency Division Multiplexing(OFDM)is the most widely used multi-carrier modulation technique.However,due to rectangular symbol shaping,OFDM system requires strict synchronization to obtain the optimal system performance.Future 5G wireless system have needs to support both conventional broadband traffic and sporadic short packet transmission.In order to reduce power consumption and synchronous signaling overhead of low-end devices,a novel non-orthogonal waveform,Universal Filtered Multi-Carrier(UFMC),has been proposed by Bell Labs.This waveform outperforms CP-OFDM when time-frequency non-perfect synchronization.In addition,UFMC filters a group of consecutive subcarriers,the order of filter can be shorter than FBMC system,which makes UFMC more suitable for short burst transmission.Based on the above background,this paper first introduces the basic model of UFMC system,analyzes the key technology in UFMC system,and then researches the influence of timing deviation and carrier frequency offset on UFMC system performance.Simulation results indicate that UFMC system is more robust against CFO and time-synchronization offset than OFDM system.An UFMC transmitter has higher complexity than OFDM system due to the subband basis filtering.In order to reduce the complexity of UFMC transmitter,this thesis investigates computational complexity of various time-domain and frequency-domain implementation methods and proposes an UFMC transmitter structure based on paratition convolution.Theory analyses results demonstrate that this approach has lower complexity and can be easily implemented on FPGA.In receiver,the frame synchronization and carrier frequency synchronization are two important steps of receiving signal processing.In this thesis,we propose an UFMC receiver synchoronization scheme based on two identical training symbols.This scheme detects frames based on delay correlation algorithm and synchronizes carriers based on maximum likelihood algorithm.According to Modelsim simulation results,this scheme can detect arrival of frames correctly and synchronize carriers at the same time.In order to complete wireless sending and receiving,this thesis designs a parameter configuration and data transmission interface control module.And the digital baseband signals generated by the FPGA are sent to RF chip through this module.At last,the UFMC processing module designed above is combined with the interface control module.Capture and analyze on-chip signals by Intergrated Logic Analyzer Pro cores.The results show that the internal signals of FPGA are consistent with the simulation results,and the performance can satisfy the design requirements.