Zynq-based Accelerator Design For Deep Convolutional Neural Networks

In recent years,Convolutional Neural Network(CNN)has become a hot topic in the field of image recognition.CNN can be used for object recognition,classification,and natural language processing,etc.In recent years,with the upgrading CNN complexity,the traditional CPU platform has been insufficient to cope with large-scale computing.GPU,FPGA and other heterogeneous computing platforms become the focus of CNN accelerator research.Among these platforms,FPGA stands out with its low energy consumption and energy efficiency comparing with GPU platform.FPGA will have broad application prospects in low-power embedded field.A convolutional neural network embedded computing accelerator design has been proposed base on Zynq platform.Software-hardware partitioning is the first conducted based on the characteristics of convolutional neural network.FPGA is employed for convolution layer calculation and ARM is responsible for pooling layer calculation,activation function calculation,as well as process control.Furthermore,under the constraints of limited on-chip resources,convolution process parallelism is analyzed.DDR access bandwidth is then maximized using tiling and reuse with reasonable parallelism.An open source CNN model,Darknet,was employed.And the design uses Fixed-Point Processing to implement calculation.ImageNet test is conducted on Zedboard development board.The results show that the accelerator's forward-propagation time is 0.57 second per image,which is 14.3 times faster than ARM-only system.The Top-5 accuracy is 80.6% on ImageNet's 50,000 pictures and the power consumption is 2.279 W,which is 20 times lower than using 2.5GHz CPU platform.