Design Of Binocular Stereo Vision Accelerator Based On FPGA

Binocular stereo vision technology is one of the important methods for constructing a three-dimensional model,and has the advantages of simple equipment,high precision,wide application scene and so on.However,the implementation of the algorithm by the general processor will cost a lot of computation time,and it is difficult to meet the real-time requirement of embedded applications.Therefore,this paper mines a parallelism in the binocular stereo vision algorithm and customizes an efficient computation pipeline for FPGA(Field Programmable Gate Array)platform to realize a complete binocular stereo vision system.In this paper,the binocular stereo vision system is mainly divided into three parts:image input part,depth extraction part and display part of processing result.In the image input part,the image used in this design is provided by Middlebury.In this design,two kinds of methods,which are suitable for bare metal and operating systems respectively,are provided for correctly storing picture data into memory.The depth extraction is the core part of this design.This paper uses Census Transform method to extract the feature information of the object in the picture,uses Hamming Distance to measure the similarity of pixels in the left and right pictures,and selects the highest similarity pixel point as the best pixel point through the method of WTA(Winner Take All).Finally,the median filter is used to reduce the noise information and retain the edge profile.In order to observe processing,result more intuitively,in the result display part,the design uses Qt creator software to draw the final processing result and outputs result to the display screen through HDMI(High Definition Multimedia Interface).The FPGA platform used in this design is a Zedboard based on the Xilinx's ZYNQ-7020.Since the ZYNQ-7020 is an SoC(System on Chip)architecture,after using an SD card to start a Linux operating system,this design puts the input part of the image and the output part of the final result into the ARM core for processing and places the depth extraction part with large amount of computation into FPGA to implement.After a actual test,under the condition that the clock frequency is 100MHz,the disparity value is 128,the parameter of Census Transform is 5*5,and the parameter of median filter is 3*3,only 6.4 milliseconds is required to process a resolution image of 704*486.However,the same algorithm takes 8.09 seconds to implement on an Intel(R)Core(TM)i5-2520M CPU with the clock frequency of 2.5GHz.So,this design achieves the purpose of acceleration and has the characteristic of real-time.