Research On TIADC Timing Error Estimation Algorithm And Hardware Inplementation

With the development of modern communication technology,there are more and more demands put on the bandwidth and precision of the signal processing.Timeinterleaved ADC is an novel analog-to-digital converter.The TIADC system employs a number of identical ADCs to form an analog to digital converter,which overcomes the contradiction between the traditional single channel ADC sampling rate and the conversion accuracy.Thus,it makes it possible to obtain high precision and high sampling rate ADC converter.Due to the deviation and the limitation in the manufacturing process,and because of the deviation of analog front-end sampling circuit.The frequency response of each channel of the Time-interleaved ADC is not completely consistent,which causes the mismatch errors among the channels.These mismatch errors mainly include: offset mismatch,gain mismatch and timing mismatch.These errors affect the overall performance of the TIADC system,such as SNDR and SFDR.There are already exits mature estimation and compensation techniques for offset mismatch and gain mismatch.The timing mismatch has become the biggest bottleneck restricting the performance of the TIADC system.This paper mainly focuses on the hardware implementation of the error estimation and compensation algorithm.The software algorithm is converted to specific RTL hardware circuits,and the hardware simulation and verification are carried out.In this paper,we first research an estimation and compensation system for sample timing mismatch error of a two channel TIADC system which based on test signal.We also carry on the implementation of the hardware RTL code and the FPGA verification.Due to the introduction of the test signal,it reduced the input signal's limits.Because the energy of the error signal is too small to calibrate the error spurs,the frequency range of the input signal is expanded.This timing error correction algorithm uses Fx LMS algorithm to iterative to get results,and the estimation and correction of errors can be carried out simultaneously with the transforming of the system.It has higher practicability and versatility.In addition,this paper also researches an efficient algorithm to estimate the mismatch error of sampling time.And it focuses on the research of hardware implementation.The error estimation algorithm is based on the phase invariance of all phase FFT transform(ApFFT)and the frequency domain sparse signal distribution of non aliasing frequency point.The hardware implementation focuses on the FFT algorithm module,the module of the square root and CORDIC algorithm module.Further more the algorithm is implemented and simulated in RTL level.At last,the corresponding algorithm is implemented and simulated.By comparing the results of MATLAB,Modelsim and verified on the FPGA development board,The effectiveness of hardware implementation is verified.These simulations provide ideas and facilities for further development of related hardware ASIC and IP.