The Design Of Digital Channel Board For Ic Tester And The Research Of Synchronization Technology

As a professional instrument for testing the chip in the integrated circuit industry,the stability and accuracy of the IC tester is self-evident.In recent years,with the rapid development of integrated circuits,the pin and speed of the chip have increased dramatically,and a higher requirement for the IC tester is also put forward.At present,there is a considerable gap between the development of domestic IC testing field and foreign technology,and it is difficult to meet the needs of the development of the times.Especially in high-speed test and high index test,the problem of multi-channel synchronization is particularly prominent.The synchronization performance of IC tester will directly affect the test data and results.Starting from the design of the digital channel board in the IC tester,this paper focuses on the problems related to the high resolution edge location and channel synchronization performance.The hardware scheme of the digital channel board is analyzed and put forward,and corresponding synchronous circuits and calibration methods are designed according to the scheme.The following aspects are mainly studied:1.The scheme of digital channel board and the design of specific circuit.According to the requirements and size constraints,a digital channel board with FPGA as control center is designed,and vector generation module,format generation module and so on are integrated into FPGA to achieve higher performance and smaller PCB area.A large capacity external memory is used on the digital channel board,which can store up to 64 M test vectors per channel.2.In order to realize the high resolution waveform edge of 40 PS,three schemes are proposed,the delay chip method,the internal delay line method and the Gigabit Transceiver method.3.From The clock circuit,the signal transmission circuit of the signal acquisition circuit about the multi-channel synchronous and other factors,analyzes their influence on the performance of synchronization,and designed the corresponding clock synchronization scheme,sending synchronization scheme,acquisition synchronization scheme,completed the design of multi channel synchronization.4.The time domain reflectometry is introduced to measure the channel delay.The test structure is compensated according to the calibration data,which eliminates the effect of signal transmission delay on the test results and improves the accuracy of the system.