Design And Verification Of Power Sequence Controller In Power Management IC

With the popularity of portable mobile devices,users’ expectation on the product quality continue to increase.Power management IC(PMIC)is an important part of a portable mobile device,and its quality is related to the quality and performance of the corresponding products,and directly affects users’ satisfaction with the product.Therefore,it is very important to design high-quality PMIC to provide quality power management products.The main chip of a portable mobile device usually requires multiple power supplies.When turn the system on,off and in other process,it is necessary to turn on or off the power in a specific sequence,and there is an interval between the control of adjacent power.If the design is not good enough,it will affect the performance of the system and even cause permanent damage to the chip.So,it is meaningful to design the power sequence.The design of the power sequence controller in this paper,is based on a portable mobile device PMIC design project,mainly used to control the power sequence when turn the system on,off and in other process.This paper analyzed the feature and requirements of system power control,and made the design realized all the control function with program.Design is realized with VHDL and the overall architecture and sub-modules of power sequence controller are designed with Top-Down design method.The final design of power sequence controller can control 3 DC-DC and 8 LDO,met the power sequence control needs when turn the system on,off and in other process.When system enters standby,it can reduce the corresponding power supply voltage to save power for system.When system exits standby,it can recover the voltage,to ensure system work normally.In addition,it can control up to 12 I/O of PMIC,and implement the communication with So C(System on Chip)and other peripheral modules during power control process.In order to ensure the correctness and completeness of the design function,this paper made a verification plan,designed a reusable testbench based on UVM verification methodology,and developed test cases with System Verilog to verify power sequence controller at module-level and system-level.In order to ensure the adequacy of verification,code coverage and functional coverage were collected during module-level verification to evaluate its quality.The simulation was performed with QUESTASIM under Linux environment.Finally,all the test cases passed,code coverage and function coverage both reached 100%,met the verification requirements.The final verification result shows that the function of power sequence controller is correct and complete,and met the design requirements.Module-level testbench can generate constrained random stimulus automatically and improved verification efficiency.The components in module-level verification environment can be reused in system-level verification,thus the work load of building system-level testbench is reduced,and the verification cycle is shortened effectively.