Research On Hardware Optimization Of Image Matching Algorithm

With the development of digital image processing technology,the digital image processing system needs more and more data to be calculated.The performance of the hardware computing device is getting higher and higher,and the real-time analysis performance of the digital image processing system becomes a research focus.The thesis takes the image matching algorithm as the research object.In order to speed up the efficiency of image matching operation,the SIFT algorithm based on image local feature detection is optimized by hardware,including the following aspects:Firstly,the principle of the SIFT algorithm is analyzed,and the hardware optimization scheme of formulating the specific steps of the algorithm is discussed.Secondly,aiming at the problem of time-consuming establishment of scale space in software algorithms,the thesis presents a pipeline hardware architecture using time-division multiplexing,which speeds up the generation of scale space significantly.Compared with other non-FPGA platform implementations,it shows that this FPGA-based optimization scheme has obvious advantages in terms of generation speed.By comparing with the performance of other FPGA-based scale space generation methods,the thesis shows that the implementation method has obvious advantages on processing speed and logical resources.Thirdly,aiming at the shortcomings of traditional reciprocal square root hardware implementation scheme,an implementation of reciprocal square root hardware based on piecewise quadratic interpolation and a Newton iteration method is proposed.And the thesis conducted experimental simulation,compared with other hardware-based solutions.