Design Of A Low Noise Amplifier For Human Biosignal Processing

In recent years,the concept of wireless body area network(WBAN)is widely concerned.It is a small communication network on the human body composed of several wireless body sensors and a central control unit.Wireless body area networks are generally used in portable,implantable and wearable medical devices.Based on the wireless body area network,we can easily monitor and share the information of human health status.The premise of constructing the wireless body area network is to obtain high quality bioelectrical signals,and to ensure the low power consumption of the whole signal acquisition system,so as to meet the demand of long-term real-time monitoring.The key to realize the above two goals lies in the low noise amplifier(LNA)with good performance,which is also the focus of this paper.In this paper,the characteristics of bioelectrical signals and the various types of noise interference,such as flicker noise,thermal noise and DC offset,are analyzed.This paper presents a low noise amplifier for low frequency physiological signals,which is composed of low noise preamplifier,programmable gain amplifier,low pass filter,Class AB amplifier,clock generation circuit and voltage reference.The amplifier has the characteristics of high input impedance,high CMRR,low noise,low power consumption.In the low noise preamplifier,this paper uses the chopper technique to suppress the flicker noise.It modulates low-frequency noise to high frequency,combined with a low pass filter,and the flicker noise is effectively reduced.On the basis of the traditional current reuse technique,a new dual channel three input current reuse technique is proposed in this paper to further optimize the noise performance of the amplifier.To solve the problem of the high impedance and DC offset brought by biological electrodes,the positive feedback capacitance and pre-charging technique are used to improve the input impedance of the amplifier,an integrator is used to form the DC offset cancellation loop.The programmable gain amplifier changes the gain by adjusting the value of the negative feedback capacitance.The low pass filter adopts Gm-C structure to achieve an ultra low cut-off frequency,with low power consumption and small size.The class-AB amplifier uses low supply voltage structure and can provide sufficient gain and drive capability.The clock generation circuit generates two phase non overlapping clocks of%50,45%and 5%duty cycles for chopping switches respectively.The voltage reference achieves zero temperature coefficient based on the temperature characteristics of sub threshold CMOS,and uses a novel offset scaling down structure.The voltage reference has the characteristics of low offset,low power consumption and low output voltage.Finally,based on the 0.18?m 1P6M standard CMOS process,this paper completes the layout design and simulation of the low noise amplifier.The simulation results show that the total power consumption per channel is 1.5?W under the supply voltage of 1.2V.In the bandwidth of 0.52 Hz to 157 Hz,the variable gain is 39.8dB~91.4dB,the equivalent input reference noise is 1.12 Vrms,the noise efficiency factor is 2.7,the low frequency input impedance is 202M?.The core area of the chip is 0.73 x 0.68mm~2...