Research On Key Technologies Of The Low Power Mixed-signal Circuit For Wireless Body Area Network

With the improvement of public health awareness and the development of large-scale integrated circuits,the wearable medical devices in WBANs provide a new protective umbrella for the nation's health.The biomedical chip is the most important part of this equipment.The design difficulties of the biomedical chip include high power consumption,complex functions,high performance,and high reliability.Therefore,this paper mainly focuses on the low-power design methods and key technologies of critical circuits in biomedical chips.The specific research contents are as follows:Aiming at the requirements of the biomedical chip for linear and load regulation,PSRR at low-frequency and transient response,the cross-coupling Class-AB push-pull input stage is proposed to improve the output impedance,and thus the loop gain of the whole LDO is boosted.By checking and feedbacking output change,the sub-threshold transient enhancement circuit works from the subthreshold region to the saturation region,generating a large current to pull-down the gate voltage of the power PMOS.Hence,undervoltage and recovery time can be reduced.Simulation result in SMIC 0.18?m CMOS process shows that the proposed LDO area is 156.3?m×98?m.At 1.2V supply,the maximum output current and the maximum load capacitance are 100 m A and 100 p F respectively.Meanwhile,the static current at full-load and no-load is 41.8?A and 43?A,respectively and the transient quality factor Fo M is 0.08 ps with 99.96% efficiency.Two novel switching schemes are presented to lower capacitor array area,switching energy,and comparator dynamic offset voltage.In a two-step switching scheme,the coarse quantization uses the variable resolution switching scheme to decrease the switching energy in the high bits generation process while the fine applies the monotone switching scheme to reduce the switching energy in low bits generation process.The C-2C structure is employed to lower capacitor array area.Benefit from the sampling halving switching scheme,it only uses the Vcm reference which is good for SAR ADC energy efficiency.Secondly,in order to improve the comparator speed at low supply,the body-driven and the back-to-back inverter are proposed to enhance the positive feedback of the comparator,which shortens the comparator delay.Cascode current source is used to suppress the dynamic offset voltage.Simulation results in 0.18?m 1P6 M standard CMOS process show that the effective area of the SAR ADC is 700um×340um.SAR ADC consumes 30.4n W,and SNDR and SFDR are 58.75 d B and 69.28 d B respectively with a Fo M of 4.32 f J /Conversion step at 0.4V.Aiming at high power consumption,large area,and poor filter performance in aliasing filter,based on the discrete-time analog computation concept,this paper proposed an analog 9-tap FIR filter.The multiplier which can achieve multiplication,consists of the PMOS transistors,instead of the NMOS transistors to suppress the 1/f noise and the substrate noise.Meanwhile,the multiplier works in the sub-threshold region,which lowers power consumption.Timedomain interleaving technology is adopted to implement the delay function.The switch rotation matrix is introduced to realize the same function as the same order digital FIR filter to avoid the Sinc function.Simulation results in SMIC 0.18?m 1P6 M 1.8V standard CMOS process show that the multiplier consumes only 77 n W with a bandwidth of 1.4MHz and less than 4% THD at 0.6V supply and 100 f F load capacitor.The analog 9-tap FIR filter dissipates 750 n W and 625um×345um core area at 1MHz and 100 f F load capacitor.The FIR filter has 7.42-bit ENOB in 100 KHz bandwidth and a cutoff frequency of 350 KHz with >30d B outof-band suppression with 0.6V supply.Power is reduced by 72.2% compared to the same tap digital FIR filter.Aiming at the 9-tap analog FIR filter of small input amplitude,low output precision,and attenuation,the IIR filter adopts the filter's charge sharing technology to realize a high linearity multiplier which improves the input amplitude and SNR.The output attenuation is avoided due to the IIR filtering.Multi-channel time-domain interleaving technology is adopted to effectively optimize the frequency characteristics of the filter,and to improve the speed of the SAR ADC.Measurement results in TSMC 40 nm 1P8M CMOS process show that the area of the entire chip is 1mm×1mm,and the total area of the analog 13th-order IIR filter and SAR ADC is 280?m×240?m.The 13-order analog IIR filter consumes 38.06?W at 1.1V.The IIR filter has a sampling rate of 40 MHz,a bandwidth of 1MHz,a cut-off frequency of 5MHz with > 40 d B out-of-band suppression,and an IMD3 of-63.8d B.When the sampling rate is 10 MHz,the SAR ADC consumes 54.2?W,with a Fo M of 7.93 f J/Conv.-step.INL and DNL are all within ±1LSB,which means no error and missing codes.Hence,the whole mixed-signal circuit meets the 10-bit accuracy of the biomedical chip.