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Research On Minimum Energy Design Optimization For Low-voltage Circuit

Posted on:2018-06-17Degree:MasterType:Thesis
Country:ChinaCandidate:J X NieFull Text:PDF
GTID:2348330542451647Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The bottleneck of energy consumption is critical to many consumer electronic applications.As the supply voltage continues to decrease,the dynamic energy consumption decreases in a square relationship per cycle,while the consumption of leakage energy increases exponentially per cycle.This paper focuses on the optimization method of minimum energy for low-voltage circuitIn order to realize the minimum energy design of the circuit,the energy consumption of CMOS digital circuit was modeled firstly.In this process,the near-threshold conduction current model and the process-related parameters of the unit delay model are extracted by SMIC 40nm LVT process by least squares fitting method on the basis of many scholars' research.In addition,based on the BSIM4 model,a new capacitance model with supply voltage is established by reasonable assumptions and approximations.Secondly,a new minimum energy design flow was presented.The process realization is divided into three parts:(1)constructing the cell size library;(2)calculating the "size" of the design with the switching information and the cell size library;(3)Take the design "size" into energy model to calculate the energy consumption.The unit size library includes gate capacitance size library,diffusion capacitance size library and equivalent wide size library.Finally,3 modes' ARM Cortex M3 circuit were designed using the minimum energy design flow.The three modes are run time:sleep time = 9:1/5:5/1:9.The predicted values of the supply voltages at the minimum energy for these three modes are 0.40 V,0.47 V and 0.58 V,respectively,and the energy consumptions are 2.95 pJ/cycle,1.88 pJ/cycle and 0.46 pJ/cycle.Based on the Siliconsmart software,3 standard cell libraries of 0.40 V,0.47 V and 0.58 V at the TT process corner were established for the SMIC 40 nm process.Based on the new low voltage standard cell libraries,the standard ASIC design flow were used to analyze the static timing and power consumption of the ARM Cortex M3 circuit.The energy consumption of the circuit in the three modes are 3.22 pJ/cycle,1.98 pJ/cycle and 0.51 pJ/cycle,the error between the prediction results and simulation results were 8.38%,5.05%and 9.80%respectively.
Keywords/Search Tags:digital CMOS circuit, low voltage, minimum energy
PDF Full Text Request
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