Design Of 2.4 GHz Low-power CMOS LNA For WSN Applications

The powerful sensing ability and flexible self-organized network of wireless sensor network have attracted more and more attentions.As the key part of wireless sensor network node,RF transceiver module has a high research value.With the high requirement of low power Low Noise Amplifier(LNA),as a key module in the RF transceiver chip,its performance will directly affect the RF transceiver module or even the entire performance of the wireless sensor network node.Based on the analysis and comparison of several common LNA structures,a two-stage cascade multiplexing low-noise amplifier structure is adopted,in which the current reuse technique reduces the circuit power consumption.The LC parallel network is used to replace the low noise amplifier inter-stage large inductance,thus reducing the chip area.The multiple gated transistor is used to improve the linearity of the LNA.The circuit design,pre-simulation,layout design,post-simulation and test are included in this paper.In the TT process corner and at temperature of 27 ?,the post-simulation results show that under supply voltage 1.8V the core circuit power consumption of 2.2mW,power gain of 19dB,noise figure were 3.3dB,input 1dB compression point of-19.7dBm.The low performance low noise amplifier designed in this paper has good performance parameters and can be applied to WSN RF transceiver chip.