Design Of DMIC For PPA Analysis And Optimization

With the popularization of the mobile device.Not only smartphone has been widely used but also wearable device become more popular.Voice control instead of touch control has been designed to variety mobile devices in taking photos,navigation system,or waking up system.The new technology that Automatic Speech Recognition and Voice Control System bring good opportunities and great challenges to the development of mobile devices and telecommunication fields.However,it has become a serious issue in the development of mobile devices especially in wearable devices with great power consumption to collect plenty voice signals during longtime.This article focus on the low power design of Digital Microphone Integrated Circuit which used in wearable devices.The main feature of DMIC is continuously collecting voice signals,modulating the voice signals,buffering data and communicating with Digital Signal Processor.This article makes analysis on low power digital IC design methodology and make further power consumption analysis about DMIC.Based on this,DMIC design back ground IC that SoC and PMIC are introduced.In common situation,DMIC is always integrated in SoC with large amount of power consumption.But in the wearable application the power consumption has a critical limitation.This paper proposes integrate DMIC to PMIC.And DMIC framework has been defined by using Multi-Power,Clock Gating technology and new waking up DSP logic by which DSP is woken up per 20 milliseconds.DMIC overall design defined includes three main parts which are voice data memory,DMIC controller and external communication interfaces.And the detailed design of each internal modules are described by Hardware Description Language.Meanwhile,a verification platform has been build based on UVM methodology,and functional verification done by using Questasim Tool.Then based on Intel 65 nm standard cell library,the paper uses Design Compiler(DC)to complete logic synthesis and estimate area and power consumption.Based on the result of synthesis,customize SRAM to reduce internal memory of DMIC.Finally obtain a function well,performance,power and area balanced DMIC design.On the one hand,in top-level design,DMIC is integrated in PMIC,it locates in PMIC Always on Power Domain and Real Time Clock(RTC)Domain.Instead DSP locates in SoC Switch off Power Domain,the power of DSP will be switch off while it doesn't work.Moving DMIC outside SoC can reduce the power consumption of extra clock toggle and power delivery rails;meanwhile,in order to cut power consumption,20 ms counter is set to wake up DSP when it's in sleep mode.On the other hand,in RTL level design,not only customized low power SPI interface is include,but also customized SRAM and Grey code used to optimize memory power consumption.In summarize,by using system level and RTL level low power design methodology,the power consumption of DMIC reduce from 250 mW to 25 mW.