Design And Verification Of Multithreading Core Based On RISC Architecture

The hardware multithreading framework is one of the main thread level parallel methods in the computer architecture.By adding a small amount of logical resources,the single kernel can be mapped to several logical cores,so that the processor can execute more than one thread at the same time.Based on MIPS32 instruction set,designed one microprocessor,On this basis,mapped it to four logical cores by adding a number of thread contexts and sharing the whole pipeline,it Allows instructions of multiple threads to be executed within the processor.On the basis of deep research and summarization of simultaneous multithreading structure,a multithreading micro structure is proposed,which is applied to the core of RISC processor.Designed and implemented the hardware multithreading microprocessor which can run four threads at the same time.Four program counter is set up for the processor,and the switch of each thread is completed by a thread controller.Each thread has a separate regfile.Designed four pipeline registers to save result of each stage.The decoder,ALU and memory controller are all shared.All the modules are completed by Verilog HDL.To verify the RTL code,created all kinds of test cases to complete the function of the directional test,and built a verification platform inherited from UVM verification methodology in System Verilog to complete the large-scale random test,constructed coverpoints of critical modules in order to collecting function coverage.The hardware multithreading microprocessor was synthesized under TSMC 40nm process using Design Compiler of Synopsys,the clock frequency reached 550MHz,while running four threads greatly improved the throughput and parallelism of the processor.