The Design And Implementation Of FC Switch Switching Circuit Based On Distributed Scheduling

With the rapid development of network technology,more and more people will be a variety of data information stored on the network in different form,to achieve data sharing with the people around you.The rapid expansion of information on the network capacity,the network storage technology put forward higher requirements.Storage area network technology as one of the ways to achieve network storage has the advantages of data sharing and unified data storage etc,it has become a hot research at home and abroad.Low latency,high speed and low error rate of fiber channel protocol can satisfy the storage area network requirement.Therefore,most storage area network are constructed based on the fiber channel protocol.In the structure of storage area network,FC switch is the core equipment.On the basis of fiber channel protocol,this paper firstly analyzes FC switch implementation protocol hierarchy.Then introduced the structure of FC switch,The architecture of FC switch divided into exchange layer of frames and layer of management,the main work of this paper is to design and implement switching circuit of frame exchange layer.Through discussion of queuing form and switch fabric,this paper uses VOQ form of input queueing and switch fabric uses Buffered-Crossbar switch fabric.Scheduling algorithms has a very important influence for switch performance.Degree of difficulty hardware implementation and performances of algorithms are key factors to measure scheduling algorithm.This paper use OPNET software to model switching circuit,then under uniform traffic and ON-OFF burst traffic to simulate several commonly scheduling algorithm current.Finally,considering the algorithm performance and the degree of hardware implementation difficulty,input scheduling algorithm use LQD_RR scheduling algorithm,output scheduling algorithm uses RR scheduling algorithm.Switching circuit is divided into routing module,input buffer module,input scheduling algorithm,switch fabric and output scheduling algorithm five parts in the paper.The route module extracts D_ID field,and control frames into VOQ,input scheduling algorithm reads data in the VOQ,and control data stored in the cache of switch fabric,output scheduling algorithm reads data frame from switch fabric,and output to the output port.This paper use Verilog language to describe each module of switching circuit in RTL level and make functional simulation with Modelsim software,the simulation results show that the design of each module is correct,then connecting each functional module to simulate,the results show that the overall design of switch circuit is correct.Finally,under the environment of the Quartus II to synthesize,using Alter Cyclone IV E FPGA development board to verify.Through timing analyze,the maximum frequency can reach 80.72 MHz,meeting the design requirements of 53.125 MHz clock frequency in the paper.And consistent with input data frame and output data frame by SignalTap crawled,thus proving that switching circuit is correct in hardware design.