Research On Performance And Reliability Improvement Of NAND Flash Controller

During the past decade,flash-based SSDs have been widely used in the embedded systems,PDAs,servers,supercomputers,databases etc.,because of their fast random access,low power consumption,small size and high resistance to shock and vibration.And the flash controller is one of the most critical components in SSD,it is dedicated to controlling all the operations on flash memory and is generally located between the FTL and flash chip array.For its crucial role in determining the performance of the SSD as a whole,flash controller is seen as a core technique to most commercial corporations.However,current flash controllers of SSDs have many deficiencies both at performance and reliance: the data bus bandwidth is dramatically restricted by the traditionally asynchronous interface;the potential parallelism in the flash storage array has not been efficiently explored;scalability is not good enough;the retention-associated errors are still not addressed.In this dissertation,we do some researches on the above-mentioned issues on flash controllers.At the aspect of performance,we propose three schemes to boost the throughput of flash controller: 1)we replace the ONFI asynchronous interface with source synchronous interface;2)we incorporate a MOVE instruction into existing instruction set to service the garbage collection actions;3)we propose a dynamic scheduling scheme to aggressively explore the target level parallelism.The experimental results suggest that the performance of our flash controller is 4.6 to 9.4 times better than the traditional asynchronous controller as for organization of 8 channels x 8 targets.Moreover,our flash controller can scale to arbitrary number of channels and 32 targets at most per channel with high growth rate of performance.At the aspect of reliability,we implement a highly parameterizable ECC module based on BCH code to correct random errors in flash memory.The simulation results show that this ECC module can complete both the encoding and decoding task.When the information bits reach at 4096 bits with up to 12 bits errors correctable,the highest frequency can reach at 190 M Hz.Moreover,we also propose a flash scrubbing scheme,which means to scan the blocks with long retention time and either correct the potential errors or append a scrubbing tag on the OOB area of flash pages.